公开(公告)号：US20230004497A1

公开(公告)日：2023-01-05

申请号：US17872744

申请日：2022-07-25

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Isam Wadih AKKAWI ,  Venkata Subhash Reddy PEDDAMALLU ,  Pratap SUBRAHMANYAM

IPC: G06F12/0862

Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.

公开(公告)号：US20230028825A1

公开(公告)日：2023-01-26

申请号：US17531582

申请日：2021-11-19

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM

IPC: G06F8/656 ,  G06F9/38 ,  G06F9/30 ,  G06F9/455 ,  G06F13/16

Abstract: A device tracks accesses to pages of code executed by processors and modifies a portion of the code without terminating the execution of the code. The device is connected to the processors via a coherence interconnect and a local memory of the device stores the code pages. As a result, any requests to access cache lines of the code pages made by the processors will be placed on the coherence interconnect, and the device is able to track any cache-line accesses of the code pages by monitoring the coherence interconnect. In response to a request to read a cache line having a particular address, a modified code portion is returned in place of the code portion stored in the code pages.

公开(公告)号：US20230069152A1

公开(公告)日：2023-03-02

申请号：US17411792

申请日：2021-08-25

Applicant: VMware, Inc.

Inventor： Isam Wadih AKKAWI ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM ,  Nishchay DUA ,  Adarsh Seethanadi NAYAK ,  Venkata Subhash Reddy PEDDAMALLU ,  Irina CALCIU

IPC: G06F12/0804 ,  G06F13/16 ,  G06F13/40

Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

公开(公告)号：US20230023256A1

公开(公告)日：2023-01-26

申请号：US17488028

申请日：2021-09-28

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM

IPC: G06F12/084

Abstract: A method of performing a copy-on-write on a shared memory page is carried out by a device communicating with a processor via a coherence interconnect. The method includes: adding a page table entry so that a request to read a first cache line of the shared memory page includes a cache-line address of the shared memory page and a request to write to a second cache line of the shared memory page includes a cache-line address of a new memory page; in response to the request to write to the second cache line, storing new data of the second cache line in a second memory and associating the second cache-line address with the new data stored in the second memory; and in response to a request to read the second cache line, reading the new data of the second cache line from the second memory.

公开(公告)号：US20230022096A1

公开(公告)日：2023-01-26

申请号：US17383342

申请日：2021-07-22

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM

IPC: G06F21/53 ,  G06F21/54 ,  G06F21/55 ,  G06F9/455 ,  G06F12/0891

Abstract: While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.

公开(公告)号：US20230004496A1

公开(公告)日：2023-01-05

申请号：US17367048

申请日：2021-07-02

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Isam Wadih AKKAWI ,  Venkata Subhash Reddy PEDDAMALLU ,  Pratap SUBRAHMANYAM

IPC: G06F12/0862

Abstract: Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.

公开(公告)号：US20220414017A1

公开(公告)日：2022-12-29

申请号：US17355941

申请日：2021-06-23

Applicant: VMware, Inc.

Inventor： Nishchay DUA ,  Andreas NOWATZYK ,  Isam Wadih AKKAWI ,  Pratap SUBRAHMANYAM ,  Venkata Subhash Reddy PEDDAMALLU ,  Adarsh Seethanadi NAYAK

IPC: G06F12/0897 ,  G06F12/0831 ,  G06F12/0862 ,  G06F9/455

Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.