公开(公告)号：US20190114092A1

公开(公告)日：2019-04-18

申请号：US15785214

申请日：2017-10-16

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Aasheesh KOLLI

IPC: G06F3/06 ,  G06F12/128 ,  G06F12/0871 ,  G06F12/0811

Abstract: The disclosure provides an approach for testing if a cache line of a cache has been flushed to non-volatile memory (NVM). The approach generally includes reading, by a central processing unit (CPU), data from the NVM. The approach further includes storing, by the CPU, a copy of the data in the cache as a cache line. The approach further includes modifying, by the CPU, at least a portion of the copy of the data in the cache. The approach further includes requesting, by the CPU, the cache line be flushed to the NVM. The approach further includes performing, by the CPU, one or more instructions in parallel to the cache line being flushed to the NVM. The approach further includes requesting, by the CPU, a state of the cache line and determining if the cache line has been persisted in the NVM based on the state of the cache line.

公开(公告)号：US20230004497A1

公开(公告)日：2023-01-05

申请号：US17872744

申请日：2022-07-25

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Isam Wadih AKKAWI ,  Venkata Subhash Reddy PEDDAMALLU ,  Pratap SUBRAHMANYAM

IPC: G06F12/0862

Abstract: A method of prefetching memory pages from remote memory includes detecting that a cache-line access made by a processor executing an application program is an access to a cache line containing page table data of the application program, identifying data pages that are referenced by the page table data, initiating a fetch of a data page, which is one of the identified data pages, and starting a timer. If the fetch completes prior to expiration of the timer, the data page is stored in a local memory. On the other hand, if the fetch does not complete prior to expiration of timer, a presence bit of the data page in the page table data is set to indicate that the data page is not present.

公开(公告)号：US20200233804A1

公开(公告)日：2020-07-23

申请号：US16255432

申请日：2019-01-23

Applicant: VMware, Inc.

Inventor： Jayneel GANDHI ,  Pratap SUBRAHMANYAM ,  Irina CALCIU ,  Aasheesh KOLLI

IPC: G06F12/0853 ,  G06F12/1045 ,  G06F12/1009 ,  G06F12/0804 ,  G06F12/0817

Abstract: Described herein is a method for tracking changes made by an application. Embodiments include determining, by a processor, a write-back of a cache line from a hardware unit associated with a socket of a plurality of sockets to a page table entry of a page table in a memory location associated with the processor. Embodiments include adding, by the processor, the cache line to a list of dirty cache lines. Embodiments include, for each respective cache line in the list of dirty cache lines, identifying, by the processor, a memory location associated with a respective socket of the plurality of sockets corresponding to the respective cache line and updating, by the processor, an entry of a page table replica at the memory location based on the respective cache line.

公开(公告)号：US20200034176A1

公开(公告)日：2020-01-30

申请号：US16048183

申请日：2018-07-27

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Jayneel GANDHI ,  Aasheesh KOLLI ,  Pratap SUBRAHMANYAM

IPC: G06F9/455 ,  G06F12/0862 ,  G06F12/0815 ,  G06F15/173

Abstract: Disclosed are embodiments for migrating a virtual machine (VM) from a source host to a destination host while the virtual machine is running on the destination host. The system includes an RDMA facility connected between the source and destination hosts and a device coupled to a local memory, the local memory being responsible for memory pages of the VM instead of the source host. The device is configured to copy pages of the VM to the destination host and to maintain correct operation of the VM by monitoring coherence events, such as a cache miss, caused by the virtual machine running on the destination host. The device services these cache misses using the RDMA facility and copies the cache line satisfying the cache miss to the CPU running the VM. The device also tracks the cache misses to create an access pattern that it uses to predict future cache misses.

公开(公告)号：US20230069152A1

公开(公告)日：2023-03-02

申请号：US17411792

申请日：2021-08-25

Applicant: VMware, Inc.

Inventor： Isam Wadih AKKAWI ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM ,  Nishchay DUA ,  Adarsh Seethanadi NAYAK ,  Venkata Subhash Reddy PEDDAMALLU ,  Irina CALCIU

IPC: G06F12/0804 ,  G06F13/16 ,  G06F13/40

Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.

公开(公告)号：US20230023256A1

公开(公告)日：2023-01-26

申请号：US17488028

申请日：2021-09-28

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM

IPC: G06F12/084

Abstract: A method of performing a copy-on-write on a shared memory page is carried out by a device communicating with a processor via a coherence interconnect. The method includes: adding a page table entry so that a request to read a first cache line of the shared memory page includes a cache-line address of the shared memory page and a request to write to a second cache line of the shared memory page includes a cache-line address of a new memory page; in response to the request to write to the second cache line, storing new data of the second cache line in a second memory and associating the second cache-line address with the new data stored in the second memory; and in response to a request to read the second cache line, reading the new data of the second cache line from the second memory.

公开(公告)号：US20230022096A1

公开(公告)日：2023-01-26

申请号：US17383342

申请日：2021-07-22

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Pratap SUBRAHMANYAM

IPC: G06F21/53 ,  G06F21/54 ,  G06F21/55 ,  G06F9/455 ,  G06F12/0891

Abstract: While an application or a virtual machine (VM) is running, a device tracks accesses to cache lines to detect access patterns that indicate security attacks, such as cache-based side channel attacks or row hammer attacks. To enable the device to detect accesses to cache lines, the device is connected to processors via a coherence interconnect, and the application/VM data is stored in a local memory of the device. The device collects the cache lines of the application/VM data that are accessed while the application/VM is running into a buffer and the buffer is analyzed for access patterns that indicate security attacks.

公开(公告)号：US20230004496A1

公开(公告)日：2023-01-05

申请号：US17367048

申请日：2021-07-02

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Andreas NOWATZYK ,  Isam Wadih AKKAWI ,  Venkata Subhash Reddy PEDDAMALLU ,  Pratap SUBRAHMANYAM

IPC: G06F12/0862

Abstract: Memory pages of a local application program are prefetched from a memory of a remote host. A method of prefetching the memory pages from the remote memory includes detecting that a cache-line access made by a processor executing the local application program is an access to a cache line containing page table data of the local application program, identifying data pages that are referenced by the page table data, and fetching the identified data pages from the remote memory and storing the fetched data pages in a local memory.

公开(公告)号：US20200242035A1

公开(公告)日：2020-07-30

申请号：US16256562

申请日：2019-01-24

Applicant: VMware, Inc.

Inventor： Aasheesh KOLLI ,  Irina CALCIU ,  Jayneel GANDHI ,  Pratap SUBRAHMANYAM

IPC: G06F12/0817

Abstract: Described herein is a method for tracking changes to memory locations made by an application. In one embodiment, the application decides to start tracking and sends a list of virtual memory pages to be tracked to an operating system via an interface. The operating system converts the list of virtual memory pages to a list of physical addresses and sends the list of physical addresses to a hardware unit which performs the tracking by detecting write backs on a coherence interconnect coupled to the hardware unit. After the application ends tracking, the application requests a list of dirty cache lines. In response to the request, the operating system obtains the list of dirty cache lines from the hardware unit and adds the list to a buffer that the application can read. In other embodiments, the operating system can perform the tracking without the application making the request.

公开(公告)号：US20200034297A1

公开(公告)日：2020-01-30

申请号：US16048180

申请日：2018-07-27

Applicant: VMware, Inc.

Inventor： Irina CALCIU ,  Jayneel GANDHI ,  Aasheesh KOLLI ,  Pratap SUBRAHMANYAM

IPC: G06F12/0817

Abstract: A device is connected via a coherence interconnect to a CPU with a cache. The device monitors cache coherence events via the coherence interconnect, where the cache coherence events relate to the cache of the CPU. The device also includes a buffer that can contain representations, such as addresses, of cache lines. If a coherence event occurs on the coherence interconnect indicating that a cache line in the CPU's cache is dirty, then the device is configured to add an entry to the buffer to record the dirty cache line.