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公开(公告)号：US20210142160A1
公开(公告)日：2021-05-13
申请号：US16679089
申请日：2019-11-08
申请人： NVIDIA Corporation
发明人： Sina Mohseni , Mandar Manohar Pitale , Jay Yadawa
摘要： Apparatuses, systems, and techniques to identify out-of-distribution input data in one or more neural networks. In at least one embodiment, a technique includes training a first portion of a neural network in a first set of data, and training a second portion of the neural network on a second set of data, where the first and second sets of data are similar within a first range.
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公开(公告)号：US20210141644A1
公开(公告)日：2021-05-13
申请号：US17255791
申请日：2019-05-21
申请人： VSORA
摘要： A data processing method comprising: a control unit, at least one ALU, a set of registers, a memory and a memory interface. The method comprises: a) obtaining the memory addresses of the operands; b) reading the operands from memory; c) transmitting an instruction to execute computing operations to the ALU without any addressing instruction; d) executing all of the elementary operations by way of the ALU receiving, at input, each of the operands from the registers; e) storing the data forming results of the processing operation on the registers; f) obtaining a memory address for each of the data forming a result of the processing operation; g) writing the results to memory for storage and via the memory interface, by way of the obtained memory addresses.
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公开(公告)号：US20210141605A1
公开(公告)日：2021-05-13
申请号：US17154905
申请日：2021-01-21
发明人： Fabio Indelicato
摘要： An arithmetic logic unit (ALU) including a binary, parallel adder and multiplier to perform arithmetic operations is described. The ALU includes an adder circuit coupled to a multiplexer to receive input operands that are directed to either an addition operation or a multiplication operation. During the multiplication operation, the ALU is configured to determine partial product operands based on first and second operands and provide the partial product operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide an output having a value equal to a product of the first operand second operands. During an addition operation, the ALU is configured to provide the first and second operands to the adder circuit via the multiplexer, and the adder circuit is configured to provide the output having a value equal to a sum of the first and second operands.
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公开(公告)号：US20210132911A1
公开(公告)日：2021-05-06
申请号：US17125488
申请日：2020-12-17
申请人： SK hynix Inc.
发明人： Choung Ki SONG
摘要： An arithmetic device includes a function storage circuit and an activation function (AF) circuit. The function storage circuit stores and outputs a function selection signal, a first function information signal, and a second function information signal. The AF circuit generates an activation function result data by applying a slope value and a maximum value to a multiplication/accumulation (MAC) result data in a function setting mode that is activated by the function selection signal. The slope value is set based on the first function information signal, and the maximum value is set based on the second function information signal.
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公开(公告)号：US20210096877A1
公开(公告)日：2021-04-01
申请号：US16583969
申请日：2019-09-26
发明人： Bin HE , Michael MANTOR , Jiasheng CHEN
摘要： An arithmetic logic unit (ALU) pipeline of a processing unit collapses execution bubbles in response to a stall at a stage of the ALU pipeline. An execution bubble occurs at the pipeline in response to an invalid instruction being placed in the pipeline for execution. The invalid instruction thus consumes an available “slot” in the pipeline, and proceeds through the pipeline until a stall in a subsequent stage (that is, a stage after the stage executing the invalid instruction) is detected. In response to detecting the stall, the ALU continues to execute instructions that are behind the invalid instruction in the pipeline, thereby collapsing the execution bubble and conserving resources of the ALU.in response to a stall at a stage of the ALU pipeline.
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公开(公告)号：US20210073944A1
公开(公告)日：2021-03-11
申请号：US16565088
申请日：2019-09-09
申请人： Nvidia Corporation
发明人： Shiqiu Liu , Matthieu Le , Andrew Tao
摘要： Apparatuses, systems, and techniques to enhance video are disclosed. In at least one embodiment, one or more neural networks are used to create a higher resolution video using upsampled frames from a lower resolution video.
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67.发明申请公开(公告)号：US20210064339A1
公开(公告)日：2021-03-04
申请号：US16847872
申请日：2020-04-14
发明人： YONGHWAN KIM , WOOK KIM , JAEJOON KIM , SUNGJU RYU
摘要： An arithmetic circuit includes an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals based on the plurality of input signals; a first ripple carry adder (RCA) performing a first part of an accumulation operation on the first addition signals to generate a carry; a flip-flop; a second RCA performing a second part of the accumulation operation on the second addition signals and an output of the flop-flop; the first RCA latching the carry in the flip-flop after the accumulation operation is performed; and an output buffer latching an output signal of the first RCA and an output signal of the second RCA, and outputting a sum signal representing a sum of the plurality of input signals.
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公开(公告)号：US20210048991A1
公开(公告)日：2021-02-18
申请号：US16539989
申请日：2019-08-13
申请人： NVIDIA Corporation
发明人： David Eldon Tanner
摘要： Apparatuses, systems, and techniques to detect a manner in which to optimize execution of a matrix operations. In at least one embodiment, a computer system detects a matrix operation and fetches data for the matrix operation before the matrix operation is fetched.
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公开(公告)号：US20210019115A1
公开(公告)日：2021-01-21
申请号：US16511085
申请日：2019-07-15
发明人： Ganesh Venkatesh , Liangzhen Lai , Pierce I-Jen Chuang , Meng Li , Vikas Chandra
摘要： Disclosed herein includes a system, a method, and a device including shift circuitry and add circuitry for performing multiplication of a first value and a second value for a neural network. The first value has a predetermined format including a first bit, and two or more second bits to represent a value of zero or 2n where n is an integer greater than or equal to 0. The device shifts, when the two or more second bits represent the value of 2n, the second value by (n+1) bits via the shift circuitry to provide a first result, selectively outputs zero or the second value, based on a value of the first bit of the first value, to provide a second result, and adds the first result and the second results via the add circuitry to provide a result of the multiplication of the first and second values.
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公开(公告)号：US10860293B2
公开(公告)日：2020-12-08
申请号：US16287564
申请日：2019-02-27
申请人： Nvidia Corporation
发明人： Jorge Albericio Latorre , Jeff Pool , David Garcia
IPC分类号： G06F7/78 , G06F7/57 , G06N3/04 , G06F16/901 , G06F17/16
摘要： Many computing systems process data organized in a matrix format. For example, artificial neural networks (ANNs) perform numerous computations on data organized into matrices using conventional matrix arithmetic operations. One such operation, which is commonly performed, is the transpose operation. Additionally, many such systems need to process many matrices and/or matrices that are large in size. For sparse matrices that hold few significant values and many values that can be ignored, transmitting and processing all the values in such matrices is wasteful. Thus, techniques are introduced for storing a sparse matrix in a compressed format that allows for a matrix transpose operation to be performed on the compressed matrix without having to first decompress the compressed matrix. By utilizing the introduced techniques, more matrix operations can be performed than conventional systems.
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