公开(公告)号：US09178081B2

公开(公告)日：2015-11-03

申请号：US13898264

申请日：2013-05-20

Applicant: CANON KABUSHIKI KAISHA

Inventor： Nobuyuki Endo ,  Tetsuya Itano ,  Kazuo Yamazaki ,  Kyouhei Watanabe ,  Takeshi Ichikawa

IPC: H01L27/146 ,  H01L31/0224 ,  H01L31/02 ,  H04N5/374

CPC classification number: H01L27/14634 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/02 ,  H04N5/374 ,  H04N5/3742

Abstract: An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer.

Abstract translation: 根据本发明的装置，其中包括具有晶体管的光电转换元件和栅电极的第一基板和包括外围电路部分的第二基板彼此放置。 第一基板不包括高熔点金属化合物层，第二基板包括高熔点金属化合物层。

公开(公告)号：US09167180B1

公开(公告)日：2015-10-20

申请号：US14324648

申请日：2014-07-07

Applicant: Raytheon Company

Inventor： Darin S. Williams ,  Martin S. Denham

IPC: H04N5/235 ,  H04N5/335 ,  H04N5/374 ,  H04N1/21 ,  H04N5/378

CPC classification number: H04N5/3355 ,  H04N1/2112 ,  H04N5/33 ,  H04N5/3742 ,  H04N5/37455 ,  H04N5/378

Abstract: The accumulation of registered sub-frame residuals in an address-mapped repartitioned digital pixel matches the intensity resolution (dynamic range) to the spatial resolution of the image. The digital accumulation of pixel quantization events (QEs) is extended to include sub-frame residuals. After all QEs are digitally accumulated, then removed from the analog accumulator, an analog residual value remains. Residual capture logic is configured to trigger residual digitization logic at least twice per frame interval for selected pixels to capture, digitize and then clear the residual value on the storage device. Memory update logic is configured to accumulate the quantization event digital values and residual digital values into existing digital values at the address-mapped memory locations in digital memory. Resolution enhancement is enabled by an address mapping that maps a one-pixel spacing on the detector to two or more pixel spacing in the digital memory.

Abstract translation: 注册的子帧残差在地址映射重新划分的数字像素中的累积将强度分辨率（动态范围）与图像的空间分辨率相匹配。 像素量化事件（QE）的数字累积被扩展到包括子帧残差。 在所有QE数字累积后，从模拟累加器中取出，剩余模拟残留值。 剩余捕获逻辑被配置为针对所选择的像素触发残差数字化逻辑至少两帧，以便捕获，数字化然后清除存储设备上的剩余值。 存储器更新逻辑被配置为在数字存储器中的地址映射存储器位置处将量化事件数字值和残余数字值累加为现有数字值。 通过地址映射来实现分辨率增强，地址映射将检测器上的一个像素间隔映射到数字存储器中的两个或更多个像素间距。

公开(公告)号：US20150296160A1

公开(公告)日：2015-10-15

申请号：US14438260

申请日：2013-10-28

Applicant: SHIMADZU CORPORATION ,  TOHOKU UNIVERSITY

Inventor： Hideki Tominaga ,  Ryuta Hirose ,  Kenji Takubo ,  Shigetoshi Sugawa ,  Rihito Kuroda

IPC: H04N5/378 ,  H04N5/376

CPC classification number: H04N5/378 ,  H01L27/14609 ,  H04N5/3692 ,  H04N5/3742 ,  H04N5/3765

Abstract: A logical gate circuit (5) and four stages of flip flips (4a-4d) are assigned to each pixel (1). A controller (7) inputs four phase identification signals into the logical gate circuit (5) and also inputs a start signal STR into a shift register (4) synchronously with the four mutually different phases defined by the phase identification signals. During one round of scanning all the pixels (1) for a readout control, if an enable signal ENBL is set to “0” while an output of a phase identification circuit (110) is “1”, a charge accumulation time at the pixel (1) concerned becomes equal to a readout period T. If the enable signal ENBL is set to “1” while the output of the phase identification circuit (110) is “1”, electric charges accumulated in a photodiode (11) until that point are entirely discarded, so that the charge accumulation time becomes shorter than the readout period T. Thus, the charge accumulation time at each pixel (1) can be controlled to ensure an adequate SN ratio while avoiding signal saturation at some pixels even if the light source has a bright line at a specific wavelength.

Abstract translation: 逻辑门电路（5）和四级翻盖（4a-4d）被分配给每个像素（1）。 控制器（7）将四个相位识别信号输入到逻辑门电路（5）中，并且与由相位识别信号定义的四个相互不同的相位同步地将起始信号STR输入到移位寄存器（4）中。 在扫描所有像素（1）的一轮扫描读出控制期间，如果在相位识别电路（110）的输出为“1”的情况下使能信号ENBL被设置为“0”，则像素处的电荷累积时间 （1）相当于读出期间T.如果在相位识别电路（110）的输出为“1”的情况下将使能信号ENBL设定为“1”，则在该光电二极管（11）中累积的电荷直到那 点被完全丢弃，使得电荷累积时间变得比读出周期T短。因此，可以控制每个像素（1）处的电荷累积时间，以确保足够的SN比，同时避免某些像素处的信号饱和，即使 光源在特定波长处具有亮线。

公开(公告)号：US09160940B2

公开(公告)日：2015-10-13

申请号：US13847551

申请日：2013-03-20

Applicant: Sony Corporation

Inventor： Satoshi Ogata ,  Rei Yoshikawa ,  Hiroaki Ebihara

IPC: H04N5/335 ,  H04N5/378 ,  H03M1/00 ,  H03M1/12 ,  H01L27/00 ,  H04N5/357 ,  H04N5/374

CPC classification number: H04N5/357 ,  H04N5/335 ,  H04N5/3742 ,  H04N5/3765 ,  H04N5/378

Abstract: A signal processing device includes a control unit that suspends supplying of a signal to an A/D conversion unit which performs A/D conversion, during an A/D conversion period in which the A/D conversion is performed on the signal that depends on an electric charge read from a pixel; and a maintenance unit that maintains a signal value of the signal in a state where the signal is supplied by the control unit to the A/D conversion unit and that supplies the maintained signal value to the A/D conversion unit in a state where the supplying of the signal to the A/D conversion unit is suspended by the control unit.

Abstract translation: 一个信号处理装置包括一个控制单元，该控制单元在A / D转换周期内暂停向执行A / D转换的A / D转换单元提供信号，该A / D转换周期对依赖于 从像素读取的电荷; 以及维护单元，其在由所述控制单元向所述A / D转换单元提供所述信号的状态下维持所述信号的信号值，并且将所述维持信号值提供给所述A / D转换单元，其状态是 控制单元暂停将信号提供给A / D转换单元。

公开(公告)号：US09143711B2

公开(公告)日：2015-09-22

申请号：US14079510

申请日：2013-11-13

Applicant: Pelican Imaging Corporation

Inventor： Andrew Kenneth John McMahon

IPC: H04N5/225 ,  H04N5/374 ,  H04N9/09 ,  H04N3/14 ,  H04N5/341

CPC classification number: H04N5/3742 ,  G06T2207/10052 ,  H04N3/1593 ,  H04N5/3415 ,  H04N9/09 ,  H04N2209/049

Abstract: Systems and methods for controlling the parameters of groups of focal planes as focal plane groups in an array camera are described. One embodiment includes a plurality of focal planes, and control circuitry configured to control the capture of image data by the pixels within the focal planes. In addition, the control circuitry includes: a plurality of parameter registers, where a given parameter register is associated with one of the focal planes and contains configuration data for the associated focal plane; and a focal plane group register that contains data identifying focal planes that belong to a focal plane group. Furthermore, the control circuitry is configured to control the imaging parameters of the focal planes in the focal plane groups by mapping instructions that address virtual register addresses to the addresses of the parameter registers associated with focal planes within specific focal plane groups.

Abstract translation: 描述了用于控制焦平面组参数作为阵列照相机中的焦平面组的系统和方法。 一个实施例包括多个焦平面，以及控制电路，被配置为控制由焦平面内的像素捕获图像数据。 此外，控制电路包括：多个参数寄存器，其中给定参数寄存器与焦点平面中的一个相关联，并且包含关联焦平面的配置数据; 以及焦平面组寄存器，其包含识别属于焦平面组的焦平面的数据。 此外，控制电路被配置为通过将寻址虚拟寄存器地址的指令映射到与特定焦平面组内的焦平面相关联的参数寄存器的地址来控制焦平面组中的焦平面的成像参数。

公开(公告)号：US09137469B2

公开(公告)日：2015-09-15

申请号：US14302516

申请日：2014-06-12

Applicant: TOHOKU UNIVERSITY ,  OLYMPUS CORPORATION

Inventor： Shigetoshi Sugawa

IPC: H04N5/374 ,  H04N5/363 ,  H04N5/3745

CPC classification number: H04N5/3742 ,  H04N5/363 ,  H04N5/37457

Abstract: Reset noise in pixels is removed. A solid-state imaging device includes pixels arranged in row and column directions, in which each of the pixels includes a charge-voltage conversion terminal for voltage-converting signal charges transferred from a photoelectric conversion element by a transfer means, and a first reset means for resetting a voltage at the charge-voltage conversion terminal; signal lines, each of which is connected to the pixels in each column; a scanning means for selecting one row among others; and constant current circuit elements for supplying constant current to the signal lines. In the device, within each selected row, each reset voltage at each charge-voltage conversion terminal and a converted voltage from transferred signal charges are read out to and stored in each signal line supplied with constant current by each constant current circuit element, and then output.

Abstract translation: 去除重置噪点（以像素为单位）。 固态成像装置包括以行和列方向布置的像素，其中每个像素包括用于通过转印装置对从光电转换元件传送的信号电荷进行电压转换的电荷电压转换端，以及第一复位装置 用于复位所述充电电压转换端子处的电压; 信号线，每条信号线连接到每列中的像素; 用于选择一行等的扫描装置; 以及用于向信号线提供恒定电流的恒流电路元件。 在该设备中，在每个选定的行内，每个充电电压转换端子处的每个复位电压和来自传送的信号电荷的转换电压被每个恒流电路元件读出并存储在由恒定电流提供的每条信号线中，然后 输出。

公开(公告)号：US09131178B2

公开(公告)日：2015-09-08

申请号：US13871768

申请日：2013-04-26

Applicant: CANON KABUSHIKI KAISHA

Inventor： Kohichi Nakamura ,  Hiroki Hiyama

IPC: H04N3/14 ,  H04N5/378 ,  H01L27/146 ,  H04N5/374 ,  H04N5/3745

CPC classification number: H04N5/378 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/1464 ,  H01L27/14641 ,  H04N5/3742 ,  H04N5/37457

Abstract: A solid-state imaging apparatus that shortens a time for reading out pixel signals of all pixels and improves the aperture ratio of pixels is provided. The solid-state imaging apparatus includes a plurality of pixels (3) arranged in a matrix along a plurality of rows and columns, in which each of the pixels includes a photoelectric conversion element and a color filter; a plurality of buffers (2) arranged with each one corresponding to a plurality of pixels; and a plurality of vertical output lines (1) arranged such that two or more of the vertical output lines (1) are arranged correspondingly to one of the columns of the pixels; in which an input node of each of the buffers is connected commonly to a plurality of pixels having color filters of different colors, and output nodes of the plurality of buffers are connected alternately to a plurality of vertical output lines.

Abstract translation: 提供了缩短用于读出所有像素的像素信号的时间并提高像素的开口率的固态成像装置。 固态成像装置包括沿着多个行和列排列成矩阵的多个像素（3），其中每个像素包括光电转换元件和滤色器; 多个缓冲器（2），其布置有与多个像素对应的每个缓冲器; 以及多个垂直输出线（1），其布置成使得两个或更多个垂直输出线（1）对应于所述像素的列之一排列; 其中每个缓冲器的输入节点共同连接到具有不同颜色的滤色器的多个像素，并且多个缓冲器的输出节点交替地连接到多个垂直输出线。

公开(公告)号：US20150226865A1

公开(公告)日：2015-08-13

申请号：US14429375

申请日：2013-08-15

Applicant: SONY CORPORATION

Inventor： Toshiyuki Nishihara ,  Hirofumi Sumi

IPC: G01T1/20 ,  H01L27/146

CPC classification number: H04N5/23232 ,  G01T1/2018 ,  H01L27/14609 ,  H01L27/14663 ,  H04N5/3742 ,  H04N5/37457 ,  H04N5/376 ,  H04N5/3765 ,  H04N5/378

Abstract: To improve a temporal resolution.An image-capturing device includes a pixel array unit and a control unit. The pixel array unit includes a plurality of pixels classified into two or more groups, wherein pixels which belong to a same group are driven at a same timing. The control unit controls driving of the pixel array unit so that a number of groups in a period of time of read-out of electrical charge is a same number in any given timing in image-capturing operation, and that a number of groups in a period of time of exposure and accumulation of electrical charge is a same number in any given timing in the image-capturing operation.

Abstract translation: 提高时间分辨率。 图像捕获装置包括像素阵列单元和控制单元。 像素阵列单元包括分为两个或更多个组的多个像素，其中属于同一组的像素以相同的定时被驱动。 控制单元控制像素阵列单元的驱动，使得在图像捕获操作中的任何给定定时中，电荷读出的时间段中的多个组是相同数量的，并且在 在图像拍摄操作的任何给定的时刻，曝光和电荷累积的时间段是相同的。

公开(公告)号：US09094628B2

公开(公告)日：2015-07-28

申请号：US14064161

申请日：2013-10-27

Applicant: Raytheon Company

Inventor： Darin S. Williams

IPC: H04N5/235 ,  H04N5/3745 ,  H04N5/347

CPC classification number: H04N5/3355 ,  H04N1/2112 ,  H04N5/33 ,  H04N5/3742 ,  H04N5/37455 ,  H04N5/378

Abstract: By adding stabilization and super-sampling to a digital pixel readout integrated circuit (ROIC), line of sight motion, that is usually costly and difficult to control, instead becomes an ally, doubling the effective FPA resolution in some systems. The base repartitioned digital pixel architecture supplements analog signal accumulation with off-pixel digital accumulation, greatly increasing dynamic range. Adding address mapping and increasing the ratio of memory locations to pixels, enables stabilization and resolution enhancement. Additional stabilization at sub-frame intervals limits the effect of latency and simplifies complex address mapping. Pixels gains are compensated in-ROIC, without requiring multipliers. A unique partitioning of functions between the ROIC and subsequent logic allows pixel biases and non-isomorphic sampling effects to be compensated off-ROIC, reducing overall system complexity and power.

Abstract translation: 通过向数字像素读出集成电路（ROIC）添加稳定和超采样，通常成本高且难以控制的视线运动变为盟友，在一些系统中增加了有效的FPA分辨率。 基本重新分配的数字像素架构补充了离散像素数字累积的模拟信号累加，大大增加了动态范围。 添加地址映射并增加内存位置与像素的比例，可实现稳定和分辨率的提升。 子帧间隔的额外稳定限制了延迟的影响，简化了复杂的地址映射。 像素增益在ROIC中得到补偿，而不需要乘法器。 ROIC和后续逻辑之间功能的独特划分允许像素偏移和非同构采样效应在ROIC之外被补偿，从而降低整体系统的复杂性和功耗。

公开(公告)号：US20150163427A1

公开(公告)日：2015-06-11

申请号：US14102463

申请日：2013-12-10

Applicant: GVBB HOLDINGS S.A.R.L

Inventor： Jeroen ROTTE ,  Peter CENTEN

IPC: H04N5/369 ,  H04N5/378 ,  H04N5/374

CPC classification number: H04N5/3698 ,  H04N5/353 ,  H04N5/3594 ,  H04N5/3742 ,  H04N5/3745 ,  H04N5/378

Abstract: An image sensor is provided. In one aspect, the image sensor includes a pixel coupled to an output line. The pixel includes a photodiode configured to generate electrical charges in response to light and a supply circuit configured to supply a voltage to the photodiode to keep a voltage of the photodiode at or above a threshold level in an integration time. In another aspect, the pixel includes a supply circuit configured to selectively supply voltage to the photodiode in a first charge holding capacity and a second charge holding capacity.

Abstract translation: 提供图像传感器。 在一个方面，图像传感器包括耦合到输出线的像素。 像素包括被配置为响应于光产生电荷的光电二极管，以及被配置为向光电二极管提供电压以将积分时间内的光电二极管的电压保持在阈值水平以上的供电电路。 在另一方面，像素包括供电电路，其被配置为在第一电荷保持容量和第二电荷保持容量中选择性地向光电二极管供电。