公开(公告)号：US20240337731A1

公开(公告)日：2024-10-10

申请号：US18747766

申请日：2024-06-19

Applicant: CANON KABUSHIKI KAISHA

Inventor： KAZUHIRO MORIMOTO

IPC: G01S7/481 ,  G01S7/4865 ,  G01S17/10 ,  H04N25/53 ,  H04N25/771 ,  H04N25/79

CPC classification number: G01S7/4816 ,  G01S7/4865 ,  G01S17/10 ,  H04N25/53 ,  H04N25/771 ,  H04N25/79

Abstract: A photoelectric conversion device includes a photoelectric conversion unit, a light value holding unit that holds light values based on signal charges generated during a first exposure period and a second exposure period having at least one of start timing and end timing different from that of the first exposure period, a comparison unit that compares the light value based on the signal charge generated during the first exposure period with the light value based on the signal charge generated during the second exposure period, and a control unit that sets a third exposure period and a fourth exposure period having at least one of the start timing and end timing different from that of the third exposure period on the basis of a comparison result of the comparison unit. The third and fourth exposure periods are less than at least one of the first and second exposure periods.

公开(公告)号：US20240334036A1

公开(公告)日：2024-10-03

申请号：US18739970

申请日：2024-06-11

Applicant: OLYMPUS MEDICAL SYSTEMS CORP.

Inventor： Shuichi TAKIE ,  Takanori SEKIDO

IPC: H04N23/50 ,  H04N23/54 ,  H04N25/79

CPC classification number: H04N23/555 ,  H04N23/54 ,  H04N25/79

Abstract: A three-dimensional circuit board connected to a back surface of a plane circuit board includes a front surface corresponding to the back surface of the plane circuit board, an upper surface and a lower surface intersecting the front surface, a first connection electrode provided on the front surface, a second connection electrode extended from the first connection electrode to the upper surface and the lower surface, and a resist layer covering the second connection electrode in each of regions on the upper surface and the lower surface and near the front surface.

公开(公告)号：US12081882B2

公开(公告)日：2024-09-03

申请号：US18080059

申请日：2022-12-13

Applicant: NIKON CORPORATION

Inventor： Takashi Kuriyama

IPC: H04N25/59 ,  H04N3/14 ,  H04N23/73 ,  H04N23/741 ,  H04N25/53 ,  H04N25/533 ,  H04N25/581 ,  H04N25/583 ,  H04N25/76 ,  H04N25/79

CPC classification number: H04N25/59 ,  H04N3/155 ,  H04N23/73 ,  H04N23/741 ,  H04N25/53 ,  H04N25/533 ,  H04N25/581 ,  H04N25/583 ,  H04N25/76 ,  H04N25/79

Abstract: Provided is an imaging unit including an imaging section that includes a pixel capable of performing charge accumulation a plurality of times in response to an imaging instruction for generating one frame of image data; a storage section that stores a pixel signal based on output from the pixel; an updating section that updates the pixel signal already stored in the storage section by performing an integration process to integrate the pixel signal output from the pixel as a result of a new charge accumulation and the pixel signal already stored in the storage section; and a control section that controls whether the updating section performs the update, for each of a plurality of pixel groups that each include one or more pixels.

公开(公告)号：US20240292124A1

公开(公告)日：2024-08-29

申请号：US18437342

申请日：2024-02-09

Applicant: CANON KABUSHIKI KAISHA

Inventor： KAN TAKAIWA ,  AIHIKO NUMATA

IPC: H04N25/62 ,  H01L27/146 ,  H04N25/13 ,  H04N25/79

CPC classification number: H04N25/62 ,  H04N25/134 ,  H04N25/79 ,  H01L27/14645

Abstract: An imaging device includes: a photoelectric conversion element including an avalanche photodiode; a generation unit configured to generate an image based on a signal acquired by the photoelectric conversion element; a first correction unit configured to correct the image based on first characteristic information on crosstalk between pixels of the photoelectric conversion element; and a second correction unit configured to perform pixel interpolation of the image based on second characteristic information for determining a crosstalk region to neighboring pixels of a specific pixel and the image.

公开(公告)号：US20240292108A1

公开(公告)日：2024-08-29

申请号：US18443556

申请日：2024-02-16

Applicant: CANON KABUSHIKI KAISHA

Inventor： RYOTA SANDO ,  AIHIKO NUMATA

IPC: H04N23/73 ,  H04N23/60 ,  H04N25/79

CPC classification number: H04N23/73 ,  H04N23/665 ,  H04N25/79

Abstract: An image capturing apparatus comprises a photoelectric conversion element configured to include an avalanche photodiode, a voltage control that controls the reverse bias voltage applied to the avalanche photodiode, and an exposure control that controls the exposure period of the photoelectric conversion element, wherein voltage control is configured to perform a change of the reverse bias voltage during a predetermined period other than the exposure periods in two consecutive frame periods, wherein the predetermined period is set by changing a blank period within two consecutive frame periods.

公开(公告)号：US20240284076A1

公开(公告)日：2024-08-22

申请号：US18435758

申请日：2024-02-07

Applicant: CANON KABUSHIKI KAISHA

Inventor： HIDEO KOBAYASHI

IPC: H04N25/78 ,  H01L27/146 ,  H04N23/667 ,  H04N25/79

CPC classification number: H04N25/78 ,  H04N23/667 ,  H04N25/79 ,  H01L27/14634

Abstract: The photoelectric conversion device includes a plurality of pixels each including a photoelectric conversion unit and an amplification unit configured to amplifies a signal based on charge generated by the photoelectric conversion unit, an output line connected to the plurality of pixels, an interconnection disposed adjacent to the output line, and a current source circuit connected to the output line and configured to supply a current to the amplification unit of the pixel via the output line. The current source circuit includes a current source transistor connected between the interconnection and a fixed voltage node, and a cascode transistor connected between the interconnection and the output line.

公开(公告)号：US20240282071A1

公开(公告)日：2024-08-22

申请号：US18415474

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Shashank Bangalore Lakshman ,  Saideep Tiku ,  Poorna Kale

IPC: G06V10/22 ,  G06T7/00 ,  H04N25/79

CPC classification number: G06V10/235 ,  G06T7/0004 ,  H04N25/79 ,  G06T2207/20081 ,  G06T2207/20084

Abstract: Customization of a deep neural network model to analyze different regions of an image at different machine vision acuity levels. A graphical user interface presents an image captured by an image sensing pixel array and receives user interactions with the image to define regions of the machine vision acuity levels. Based on the user interactions with the graphical user interface, a region mask is generated to identify the regions of pixels in the image sensing pixel array. According to the region mask, unnecessary computations of low machine vision acuity are removed from the deep neural network model to generate a customized computing model of analyzing image data, captured by the image sensing pixel array, at the machine vision acuity levels.

公开(公告)号：US20240267646A1

公开(公告)日：2024-08-08

申请号：US18637304

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: H04N25/60 ,  H04N23/617 ,  H04N23/80 ,  H04N25/78 ,  H04N25/79

CPC classification number: H04N25/60 ,  H04N23/617 ,  H04N23/80 ,  H04N25/78 ,  H04N25/79

Abstract: A method to enhance images, including: receiving, in an image processing logic circuit in an integrated circuit device, first data representative of an input image; generating, by the image processing logic circuit, input data for an inference logic circuit in the integrated circuit device; generating, by the inference logic circuit, a column of bits from the input data; performing, by the inference logic circuit using memory cells in the integrated circuit device having threshold voltages programmed to represent at least one weight matrix, operations of multiplication and accumulation, via reading concurrently rows of the memory cells selected according to the column of bits; generating, by the inference logic circuit, output data based on results of the operations multiplication and accumulation; and generating, by the image processing logic circuit using the output data, second data representative of an output image enhanced from the input image.

公开(公告)号：US20240266381A1

公开(公告)日：2024-08-08

申请号：US18635309

申请日：2024-04-15

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Shinichi MIYAKE ,  Hirofumi YAMASHITA

IPC: H01L27/146 ,  H04N25/75 ,  H04N25/778 ,  H04N25/79

CPC classification number: H01L27/1465 ,  H01L27/14605 ,  H04N25/778 ,  H04N25/79 ,  H01L27/14641 ,  H04N25/75

Abstract: An imaging element according to an embodiment of the present disclosure includes a first semiconductor substrate, and a second semiconductor substrate stacked over the first semiconductor substrate with an insulating layer interposed therebetween. The first semiconductor substrate includes a photoelectric conversion section, and a charge-holding section that holds charges transferred from the photoelectric conversion section. The second semiconductor substrate includes an amplification transistor that generates a signal of a voltage corresponding to a level of charges held in the charge-holding section. The amplification transistor includes a channel region, a source region, and a drain region in a plane intersecting a front surface of the second semiconductor substrate, and includes a gate electrode being opposed to the channel region with a gate insulating film interposed therebetween and being electrically coupled to the charge-holding section.

公开(公告)号：US12058459B2

公开(公告)日：2024-08-06

申请号：US17609438

申请日：2020-05-08

Applicant: SONY ADVANCED VISUAL SENSING AG

Inventor： Raphael Berner ,  Chistian Brändli

IPC: H04N25/75 ,  H04N25/71 ,  H04N25/771 ,  H04N25/79

CPC classification number: H04N25/75 ,  H04N25/745 ,  H04N25/771 ,  H04N25/79

Abstract: An NMOS-only operational transconductance amplifier (OTA) replaces the PMOS transistors with switched capacitor pseudo-resistors in the pixels of an optical sensor such as a dynamic vision sensor or event-based vision sensor. Thus, if a stacked CMOS image sensor (CIS) process is employed, then the upper wafer can be kept free from N-wells, while still having the complete OTA on the upper wafer. Thus, it is possible to have only one wafer-to-wafer connection per pixel. Moreover, by operating the switched capacitor pseudo-resistors as three terminal devices, the gain can further be increased.