公开(公告)号：US09432042B2

公开(公告)日：2016-08-30

申请号：US14229307

申请日：2014-03-28

Applicant: Tektronix, Inc.

Inventor： Daniel G. Knierim ,  John J. Pickerd

IPC: H03M1/12 ,  G01R23/14 ,  G01R13/02

CPC classification number: H03M1/121 ,  G01R13/0272 ,  G01R23/14 ,  H03M1/1215

Abstract: A test and measurement instrument including a splitter configured to split an input signal having a particular bandwidth into a plurality of split signals, each split signal including substantially the entire bandwidth of the input signal; a plurality of harmonic mixers, each harmonic mixer configured to mix an associated split signal of the plurality of split signals with an associated harmonic signal to generate an associated mixed signal; and a plurality of digitizers, each digitizer configured to digitize a mixed signal of an associated harmonic mixer of the plurality of harmonic mixers. A first-order harmonic of at least one harmonic signal associated with the harmonic mixers is different from an effective sample rate of at least one of the digitizers.

公开(公告)号：US20160216295A1

公开(公告)日：2016-07-28

申请号：US14971727

申请日：2015-12-16

Applicant: Tektronix, Inc.

Inventor： Daniel G. Knierim ,  Barton T. Hickman

IPC: G01R13/02 ,  H03M1/12

CPC classification number: G01R13/0272 ,  H03M1/06 ,  H03M1/1009 ,  H03M1/121

Abstract: A test and measurement instrument includes a coefficient storage facility coupled to a programmable filter. The coefficient storage facility is configured to store at least two pre-determined filter coefficient sets, and configured to pass a selected one of the at least two pre-determined filter coefficient sets to the filter based on a measurement derived using a compensation oscillator. The measurement may include clock delay and clock skew. In some examples the test and measurement instrument may additionally adjust clock delay and/or clock skew in addition to selecting appropriate filter coefficients.

Abstract translation: 测试和测量仪器包括耦合到可编程滤波器的系数存储设备。 系数存储设施被配置为存储至少两个预定的滤波器系数组，并且被配置为基于使用补偿振荡器导出的测量将所选择的至少两个预定滤波器系数组中的一个传送到滤波器。 测量可能包括时钟延迟和时钟偏移。 在一些示例中，除了选择适当的滤波器系数之外，测试和测量仪器还可以另外调节时钟延迟和/或时钟偏移。

公开(公告)号：US09362914B2

公开(公告)日：2016-06-07

申请号：US14275896

申请日：2014-05-13

Applicant: MEDIATEK INC.

Inventor： Yuan-Ching Lien

IPC: G11C27/02 ,  H03K19/0175 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03K19/0175 ,  G11C27/02 ,  G11C27/024 ,  H03M1/0836 ,  H03M1/121 ,  H03M1/1225

Abstract: A sampling circuit for sampling a signal input includes a signal generation circuit, a sampling switch and a control circuit. The signal generation circuit is arranged for generating a first control signal. The sampling switch has a control node, and is arranged for determining a sampling time of the signal input according to a signal level at the control node. The control circuit is arranged for controlling the signal level at the control node, wherein when the signal level at the control node corresponds to a first level, and before a signal level of the first control signal is changed in order to adjust the signal level at the control node to a second level, the control circuit couples the first control signal to the control node.

Abstract translation: 用于对信号输入进行采样的采样电路包括信号发生电路，采样开关和控制电路。 信号发生电路被布置用于产生第一控制信号。 采样开关具有控制节点，并且被配置为根据控制节点处的信号电平确定信号输入的采样时间。 控制电路被布置为控制控制节点处的信号电平，其中当控制节点处的信号电平对应于第一电平时，并且在第一控制信号的信号电平改变之前，以便调整信号电平在 控制节点到第二电平，控制电路将第一控制信号耦合到控制节点。

公开(公告)号：US09294112B1

公开(公告)日：2016-03-22

申请号：US14540515

申请日：2014-11-13

Applicant: ANALOG DEVICES, INC.

Inventor： Siddharth Devarajan ,  Lawrence A. Singer ,  Prawal Man Shrestha ,  Pingli Huang

IPC: H03M1/12 ,  H03M1/06 ,  H03M1/08 ,  H03M1/00

CPC classification number: H03M1/121 ,  H03M1/00 ,  H03M1/0604 ,  H03M1/0607 ,  H03M1/0609 ,  H03M1/0612 ,  H03M1/066 ,  H03M1/0836 ,  H03M1/1033 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/124

Abstract: A time-interleaved analog-to-digital converter (ADC) uses M sub-analog-to-digital converters (sub-ADCs) to, according to a sequence, sample an analog input signal to produce digital outputs. When the M sub-ADCs are interleaved, the digital outputs exhibit mismatch errors between the M sub-ADCs due to mismatches between the sub-ADCs. A more second order subtle effect is that the mismatch error for a particular digital output from a particular ADC, due to internal coupling or other such interaction and effects between the M sub-ADCs, can vary depending on which sub-ADC(s) were used before and/or after the particular sub-ADC. If M sub-ADCs are time-interleaved randomly, the mismatches between the M sub-ADCs become a function of the sub-ADC selection pattern in the sequence. The present disclosure describes mechanisms for measuring and reducing these order-dependent mismatches to achieve high dynamic range performance in the time-interleaved ADC.

Abstract translation: 时间交织的模数转换器（ADC）使用M个子模数转换器（sub-ADC），根据一个序列对模拟输入信号进行采样以产生数字输出。 当M个子ADC被交错时，由于子ADC之间的不匹配，数字输出在M个子ADC之间表现出失配误差。 更多的二阶微妙效应是，由于内部耦合或其他此类相互作用和M子ADC之间的影响，来自特定ADC的特定数字输出的失配误差可以根据哪些子ADC 在特定子ADC之前和之后使用。 如果M个子ADC随机进行时间交织，那么M个子ADC之间的失配成为序列中子ADC选择模式的函数。 本公开描述了用于测量和减少这些依赖于顺序的失配以在时间交织的ADC中实现高动态范围性能的机制。

公开(公告)号：US20160079994A1

公开(公告)日：2016-03-17

申请号：US14948875

申请日：2015-11-23

Applicant: Sunghyuk Lee ,  Hae-Seung Lee ,  Anantha Chandrakasan

Inventor： Sunghyuk Lee ,  Hae-Seung Lee ,  Anantha Chandrakasan

IPC: H03M1/06 ,  H03M1/18 ,  H03M1/46 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0609 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/181 ,  H03M1/46

Abstract: A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

Abstract translation: 时间交织（TI）模数转换器（ADC）架构采用低分辨率粗ADC通道，以奈奎斯特速率对输入模拟信号进行采样，便于定时偏移误差的背景校准，而不会中断对采样/ 转换输入信号。 粗ADC通道为多个更高分辨率TI ADC通道提供了时序参考，分别以较低的采样率采样输入信号。 将粗ADC数字输出与相应的TI ADC数字输出进行比较，可随时调整TI ADC通道的相应采样时钟，使其与粗ADC通道的采样时钟基本对齐，从而减少定时偏移误差。 在一个示例中，粗ADC输出提供相应TI ADC数字输出的最高有效位（MSB），以进一步提高转换速度并降低这些通道的功耗。

公开(公告)号：US09270292B2

公开(公告)日：2016-02-23

申请号：US14769945

申请日：2014-03-07

Applicant: Anacatum Design AB

Inventor： Rolf Sundblad ,  Emil Hjalmarsson

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/1255 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/126

Abstract: A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.

Abstract translation: 用于将模拟输入信号转换为具有采样率R的数字输出信号的时间交织的模拟 - 数字转换器包括基于模数转换器操作的N个组成模数转换器的阵列 操作时钟以提供数字输出信号，N个采样保持单元连接到基于M个定时信号中的相应一个的相应组成模数转换器的输入，其中不使用定时信号 时钟两个或更多个采样和保持单元，一个或多个数字输出处理单元，其基于相应的一个提供组成模数转换器的数字输出的采样作为数字输出信号的采样 的M个定时信号，以及定时电路，其生成模数转换器操作时钟信号，每个定时信号具有M / R周期，其中M小于或等于N.

公开(公告)号：US09225353B2

公开(公告)日：2015-12-29

申请号：US14629442

申请日：2015-02-23

Applicant: Syntropy Systems, LLC

Inventor： Christopher Pagnanelli

IPC: H03M1/12 ,  H03M3/00 ,  H03M1/08

CPC classification number: H03M3/468 ,  H03M1/0836 ,  H03M1/121

Abstract: Provided is an apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, which includes an input line for accepting an input signal, multiple processing branches coupled to the input line, and an adder coupled to outputs of the plurality of processing branches. Each of the processing branches includes a sampling/quantization circuit and a digital bandpass interpolation filter having an input coupled to an output of the sampling/quantization circuit. The digital bandpass interpolation filters in different ones of the processing branches have frequency responses that are centered at different frequencies. The digital bandpass interpolation filter in at least one of the processing branches includes: (i) a quadrature downconverter, (ii) a first lowpass filter and a second lowpass filter, (iii) a first interpolator and a second interpolator, each having an input for inputting a variable interpolant value, and (iv) a quadrature upconverter.

Abstract translation: 提供了一种用于将连续时间连续可变信号转换为采样和量化信号的装置，其包括用于接受输入信号的输入线，耦合到输入线的多个处理分支和耦合到多个输出的输出的加法器 的处理分支机构。 每个处理分支包括具有耦合到采样/量化电路的输出的输入的采样/量化电路和数字带通内插滤波器。 不同处理分支中的数字带通插值滤波器具有以不同频率为中心的频率响应。 至少一个处理分支中的数字带通插值滤波器包括：（i）正交下变频器，（ii）第一低通滤波器和第二低通滤波器，（iii）第一内插器和第二内插器，每个具有输入 用于输入可变内插值，和（iv）正交上变频器。

公开(公告)号：US09197232B1

公开(公告)日：2015-11-24

申请号：US14285026

申请日：2014-05-22

Applicant: Cable Television Laboratories, Inc.

Inventor： Belal Hamzeh

IPC: H03M1/00 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03M1/121 ,  H03M1/0854 ,  H03M1/122

Abstract: Systems and methods presented herein provide for analog to digital conversion with variable bit resolution. In one embodiment, a system includes a processor and a multiplexer. The processor is operable to receive an analog signal, to detect power spectral densities in the analog signal, to segment the analog signal into at least two frequency bands, to sample each of the frequency bands, and to quantize each of the sampled frequency bands with bit resolutions according to detected power spectral densities of the frequency bands. The multiplexer is operable to multiplex the quantized frequency bands into a data stream.

Abstract translation: 本文提出的系统和方法提供了具有可变位分辨率的模数转换。 在一个实施例中，系统包括处理器和多路复用器。 处理器可操作以接收模拟信号，以检测模拟信号中的功率谱密度，将模拟信号分段成至少两个频带，对每个频带进行采样，并用 根据检测到的频带的功率谱密度进行位分辨率。 多路复用器可操作以将量化的频带复用到数据流中。

公开(公告)号：US09178525B2

公开(公告)日：2015-11-03

申请号：US14656122

申请日：2015-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sthanunathan Ramakrishnan ,  Sreenath Narayanan Potty

IPC: H03M1/10 ,  H03M1/12 ,  H03M1/06

CPC classification number: H03M1/121 ,  H03M1/06 ,  H03M1/0626 ,  H03M1/0639 ,  H03M1/1205 ,  H03M1/1215

Abstract: A mismatch corrector can include a correction path comprising a plurality of parallel branches that each includes a correction filter that applies a respective one of a plurality of time domain filter coefficients that corresponds to a function of a mismatch profile of an interleaved analog-to-digital (IADC) signal on the IADC signal. The mismatch corrector can also include a delay path that delays the IADC signal by a predetermined number of samples to provide a delayed version of the IADC signal. The mismatch corrector can further include a summer to subtract an output of each correction filter from the delayed version of the IADC signal to generate a corrected IADC signal.

Abstract translation: 不匹配校正器可以包括校正路径，其包括多个并行分支，每个分支包括校正滤波器，校正滤波器应用与交织的模数转换器的失配曲线的函数相对应的多个时域滤波器系数中的相应一个 （IADC）信号。 不匹配校正器还可以包括将IADC信号延迟预定数量的采样以提供IADC信号的延迟版本的延迟路径。 不匹配校正器还可以包括加法器，以从IADC信号的延迟版本中减去每个校正滤波器的输出，以产生校正的IADC信号。

公开(公告)号：US09172388B1

公开(公告)日：2015-10-27

申请号：US14735386

申请日：2015-06-10

Applicant: Guzik Technical Enterprises

Inventor： Anatoli B. Stein ,  Semen P. Volfbeyn

IPC: H03M1/12 ,  H03M1/06

CPC classification number: H03M1/121 ,  H03M1/0604 ,  H03M1/0609 ,  H03M1/1023 ,  H03M1/1215

Abstract: An analog to digital conversion device with DC offset mismatch compensation comprises a composite analog to digital converter (ADC) consisting of N interleaved sub-ADCs, a DC offset accumulator, an averaging unit, a subtraction unit, and a compensation unit. The ADC generates a stream of digital samples corresponding to signal values at an analog input to the ADC. The digital stream is a combination of N partial signals produced by the respective sub-ADCs. The DC offset accumulator measures and stores DC offsets of the respective partial signals. The averaging unit calculates an average value of DC offsets of the respective N partial signals. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at a DC offset input and the value arriving at an average value input. The subtraction unit is responsive to the DC offsets of the respective partial signals and the average value of the DC offsets, to produce a signal representative of the differences between the values arriving at the DC offset input and the value arriving at the average value input. The compensation unit corrects the digital stream from the ADC by subtracting the differences from the stream from the ADC.

Abstract translation: 具有DC偏移不匹配补偿的模数转换装置包括由N个交错子ADC，DC偏移累加器，平均单元，减法单元和补偿单元组成的复合模数转换器（ADC）。 ADC在ADC的模拟输入端产生对应于信号值的数字采样流。 数字流是由各个子ADC产生的N个部分信号的组合。 DC偏移累加器测量并存储各个部分信号的直流偏移。 平均单元计算各个N个部分信号的DC偏移的平均值。 减法单元响应于相应部分信号的DC偏移和DC偏移的平均值，以产生表示到达DC偏移输入的值与达到平均值输入的值之间的差的信号。 减法单元响应于相应部分信号的DC偏移和DC偏移的平均值，以产生表示到达DC偏移输入的值与到达平均值输入的值之间的差的信号。 补偿单元通过从ADC中减去来自流的差异来校正ADC的数字流。