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    Apparatus and method for a programmable logic device having improved look up tables
    63.
    发明授权
    Apparatus and method for a programmable logic device having improved look up tables 有权
    具有改进的查找表的可编程逻辑器件的装置和方法

    公开(公告)号：US07598769B2

    公开(公告)日：2009-10-06

    申请号：US11675590

    申请日：2007-02-15

    Applicant: Vincent Leung

    Inventor： Vincent Leung

    IPC: H03K19/173

    CPC classification number: H03K19/17784 ,  H03K19/17728 ,  H03K19/17792

    Abstract: A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2N configuration bit inputs and a Look Up Table output. The first stage of the Look Up Table includes 2N tri-state buffers coupled to receive the 2N configuration bit inputs respectively. A decoder, configured from logic gates, is coupled to receive to one or more Look Up Table select signals and to generate a set of control signals to control the 2N tri-state buffers so that one or more of the 2N configuration bit inputs is selected by the first stage. The configuration bits are then provided to subsequent muxing stages in the Look Up Table.

    Abstract translation: 一种包括以阵列组织的多个逻辑元件的可编程逻辑器件。 每个逻辑元件包括具有2N个配置位输入和查找表输出的N阶查找表结构。 查找表的第一级包括2N个三态缓冲器，分别耦合以接收2N个配置位输入。 由逻辑门配置的解码器被耦合以接收一个或多个查找表选择信号并产生一组控制信号以控制2N个三态缓冲器，使得选择2N个配置位输入中的一个或多个 在第一阶段。 然后，配置位将提供给查找表中的后续多路复用阶段。

    High-performance static programmable logic array
    64.
    发明授权
    High-performance static programmable logic array 有权
    高性能静态可编程逻辑阵列

    公开(公告)号：US07474122B2

    公开(公告)日：2009-01-06

    申请号：US11668266

    申请日：2007-01-29

    Applicant: Dong-gyu Lee

    Inventor： Dong-gyu Lee

    IPC: H03K19/177

    CPC classification number: H03K19/0948 ,  H03K19/17784 ,  H03K19/17792

    Abstract: A high-performance programmable logic array (PLA) includes an AND plane that is initialized when a reset signal is activated and that evaluates a plurality of input signals when the reset signal is inactivated; and or OR plane that receives output signals of the AND plane, that is disabled when one of the output signals is activated, and that evaluates the rest of the output signals of the AND plane to output a final result signal when the one of the output signals of the AND plane is inactivated. The PLA uses a reset signal as a driving signal, instead of a clock signal. Accordingly, it is possible to realize a PLA with both low power consumption and high operation speed.

    Abstract translation: 高性能可编程逻辑阵列（PLA）包括AND平面，其在复位信号被激活时被初始化，并且当复位信号被去激活时评估多个输入信号; 和/或OR平面，其接收AND平面的输出信号，当输出信号之一被激活时被禁用，并且当输出信号中的一个输出 AND平面信号失效。 PLA使用复位信号作为驱动信号，而不是时钟信号。 因此，可以实现低功耗和高操作速度的PLA。

    Programmable semiconductor device
    65.
    发明授权
    Programmable semiconductor device 失效
    可编程半导体器件

    公开(公告)号：US07446562B2

    公开(公告)日：2008-11-04

    申请号：US11628532

    申请日：2005-05-25

    Applicant: Masahiro Nomura ,  Koichi Takeda

    Inventor： Masahiro Nomura ,  Koichi Takeda

    IPC: H01L25/00 ,  H03K19/177

    CPC classification number: H03K19/17748 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17792

    Abstract: A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.

    Abstract translation: 本发明的可编程半导体器件包括：执行预定操作的处理元件单元; 用作信号输入部分的输入/输出连接单元和/或处理元件单元中的信号输出部分; 由多根电线组成的互连单元，经由输入/输出连接单元连接处理元件单元; 双向中继器单元，布置在互连单元的交点之间，在正向或反向上执行断开或驱动互连单元; 和互连连接单元，布置在交点处，交叉点处连接互连单元。

    FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same
    66.
    发明授权
    FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same 有权
    具有混合互连资源的FPGA架构，针对快速和低功耗路由进行了优化，并采用了相同的方法

    公开(公告)号：US07138828B2

    公开(公告)日：2006-11-21

    申请号：US10941248

    申请日：2004-09-15

    Applicant: Bernard J. New

    Inventor： Bernard J. New

    IPC: H01L25/00

    CPC classification number: H03K19/17736 ,  H03K19/17784 ,  H03K19/17792

    Abstract: An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

    Abstract translation: FPGA包括可编程互连结构，其中互连资源被分成两组。 互连资源的第一个子集针对高速进行了优化。 互连资源的第二个子集针对低功耗进行了优化。 在一些实施例中，第一和第二子集的晶体管具有不同的阈值电压。 第一子集中的晶体管针对速度进行了优化，具有比第二子集中的晶体管更低的阈值电压，其针对低功耗进行了优化。 阈值电压的差异可以通过使用不同的掺杂水平，偏置到不同电压电平的阱或使用其他公知的方法来实现。 在一些实施例中，互连资源的第一子集包括耦合到比第二子集更高电压电平的缓冲器。 在一些实施例中，第一子集包括使用比第二子集中的晶体管更大的晶体管制造的缓冲器。

    High speed IO buffer using auxiliary power supply
    67.
    发明授权
    High speed IO buffer using auxiliary power supply 有权
    高速IO缓冲器采用辅助电源

    公开(公告)号：US07088140B1

    公开(公告)日：2006-08-08

    申请号：US10794987

    申请日：2004-03-04

    Applicant: Khai Nguyen ,  Chiakang Sung ,  Gopi Rangan ,  Tzung-Chin Chang

    Inventor： Khai Nguyen ,  Chiakang Sung ,  Gopi Rangan ,  Tzung-Chin Chang

    IPC: H03K19/0175

    CPC classification number: H03K19/17744 ,  H03K19/00315 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

    Abstract: Circuits, methods, and apparatus that provide output drivers that consume relatively little integrated circuit area and provide fast output switching. An exemplary embodiment provides an output driver including pull-up and pull-down devices, each device driven by a pre-driver stage. The pre-driver for the pull-down device is supplied from an auxiliary power supply, which has a higher voltage than the supply seen by the pull-up device. The pre-driver for the pull-down is biased by a voltage that tracks the higher of the auxiliary and output supplies. In some embodiments, the output driver may be part of an input/output cell. In that case, the well for the pull-up device is biased by a voltage that tracks the highest of the output supply and input received voltage, while the pull-up predriver circuit bias is the higher between the auxiliary and output supplies and the input received voltage.

    Abstract translation: 提供输出驱动器的电路，方法和装置，其消耗相对较小的集成电路面积并提供快速输出切换。 示例性实施例提供了包括上拉和下拉装置的输出驱动器，每个装置由预驱动器级驱动。 用于下拉装置的预驱动器由辅助电源供电，辅助电源的电压高于上拉装置所看到的电源电压。 用于下拉的预驱动器被跟踪较高的辅助和输出电源的电压偏置。 在一些实施例中，输出驱动器可以是输入/输出单元的一部分。 在这种情况下，上拉器件的阱被跟踪输出电源的最高电压和输入接收电压的电压偏置，而上拉预驱动电路偏置在辅助和输出电源和输入之间较高 接收电压。

    Output reporting techniques for hard intellectual property blocks
    69.
    发明申请
    Output reporting techniques for hard intellectual property blocks 有权
    硬性知识产权块的产出报告技术

    公开(公告)号：US20060114022A1

    公开(公告)日：2006-06-01

    申请号：US11002577

    申请日：2004-12-01

    Applicant: Darren van Wageningen ,  Curt Wortman

    Inventor： Darren van Wageningen ,  Curt Wortman

    IPC: H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/17732 ,  H03K19/17792

    Abstract: Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP block are able to capture the output signal. A plurality of serially coupled flip-flops store values of an HIP output signal during each period of the output signal. Logic circuitry then generates a lower frequency HIP output signal in response to the values stored in the flip-flops. Also, a flip-flop can generate a heartbeat signal that is used to determine whether a signal within an HIP block is operating properly.

    Abstract translation: 提供了用于降低来自集成电路上的硬知识产权（HIP）块的输出信号的频率的技术。 通过降低输出信号的频率，集成电路中以比HIP块低的频率工作的电路块能够捕获输出信号。 多个串联耦合的触发器在输出信号的每个周期期间存储HIP输出信号的值。 然后逻辑电路响应于存储在触发器中的值产生较低频率的HIP输出信号。 此外，触发器可以产生用于确定HIP块内的信号是否正常工作的心跳信号。

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