Compact package for electronic module
    61.
    发明授权
    Compact package for electronic module 失效
    电子模块紧凑型封装

    公开(公告)号:US5091771A

    公开(公告)日:1992-02-25

    申请号:US351760

    申请日:1989-05-15

    摘要: A very compact package for an electronic data module, which includes battery-backed memory. A two-part metal container is used, which has two shallow concave pieces which fit together. The integrated circuit (in a low-height package, such as a flat-pack or SOIC) is mounted on a very small flexible printed circuit board, which fits inside the container. Laterally spaced from the integrated circuit, on the other end of the small flexible board, the board end is sandwiched between a battery and a piece of elastic conductive material (such as conductive plastic foam). Thus, the battery is connected between one face of the container and a power conductor on the board. The piece of elastic conductive material makes contact between a data trace on the board and the other face of the container. Another trace on the board makes contact directly to the container face on which the battery's ground terminal is connected. Thus, simple wiring on the small board, using through-hole vias, suffices to route power, ground, and data lines to the integrated circuit, while providing a sealed durable package with two external contacts.

    摘要翻译: 用于电子数据模块的非常紧凑的封装,包括电池备份存储器。 使用两部分金属容器,其具有两个装配在一起的浅凹片。 集成电路(在低包装中,如扁平封装或SOIC)安装在适合容器内部的非常小的柔性印刷电路板上。 与集成电路相隔一定距离,在小型柔性板的另一端,板端被夹在电池和一块弹性导电材料(如导电塑料泡沫)之间。 因此,电池连接在容器的一个面和电路板上的电源导体之间。 弹性导电材料使板上的数据迹线与容器的另一面接触。 电路板上的另一个痕迹直接与电池接地端子连接的容器面接触。 因此,使用通孔通孔的小型板上的简单接线就足以将电源,地线和数据线路路由到集成电路,同时提供具有两个外部触点的密封耐用封装。

    Low-voltage low-power static ram
    62.
    发明授权
    Low-voltage low-power static ram 失效
    低压低功率静态压头

    公开(公告)号:US4972377A

    公开(公告)日:1990-11-20

    申请号:US351998

    申请日:1989-05-15

    申请人: Robert D. Lee

    发明人: Robert D. Lee

    摘要: A low-power low-voltage CMOS six-transistor static random access memory (SRAM), which can operate on a power supply voltage which is less than the sum of the NMOS and PMOS threshold voltages, does not include any analog or metastable sense amplifier stages. The selected cell is allowed to pull one of its bitline pair all the way down to ground. Thus, full logic levels appear on the bitline pair. Only one line of the bitline pair is connected to the following gate stage. Preferably bitline precharge transistors are connected to always pull up any unselected bitline pair.

    摘要翻译: 可以在小于NMOS和PMOS阈值电压之和的电源电压下工作的低功率低电压CMOS六晶体管静态随机存取存储器(SRAM)不包括任何模拟或亚稳读出放大器 阶段 所选择的单元格允许将其位线对之一一直拉到地。 因此,位线对上出现完整的逻辑电平。 位线对只有一条线连接到下一个门级。 优选地,位线预充电晶体管被连接以总是拉起任何未选择的位线对。

    INSPECTION SYSTEM AND GAME TOKEN
    66.
    发明公开

    公开(公告)号:US20240087403A1

    公开(公告)日:2024-03-14

    申请号:US18514088

    申请日:2023-11-20

    发明人: Yasushi Shigeta

    IPC分类号: G07F17/32 G06K19/04 G07D5/00

    摘要: An inspection system for inspecting a game token, includes: a game token assigned with code information such that an ID mark region covered with a UV ink is partially irradiated with laser light to denature or remove the irradiated part; an ultraviolet irradiation lamp for irradiating the game token with ultraviolet light for visualizing the UV ink; a UV camera configured to shoot the game token irradiated with ultraviolet light; and an inspection device configured to recognize the code information that has been visualized by the irradiation with ultraviolet light based on an image shot by the UV camera and determine authenticity of the game token.

    GAME TOKEN MONEY, METHOD OF MANUFACTURING GAME TOKEN MONEY, AND INSPECTION SYSTEM

    公开(公告)号:US20240013018A1

    公开(公告)日:2024-01-11

    申请号:US18371724

    申请日:2023-09-22

    发明人: Yasushi SHIGETA

    IPC分类号: G06K19/04 G07F17/32 G06K19/07

    摘要: A game token money includes a plurality of plastic layers laminated through thermocompression bonding including at least a colored layer in the middle to specify a value of the game token money and a pair of pale color layers laminated on both sides of the colored layer. An RFID is embedded in a layer other than the outermost layer of the plurality of plastic layers; and a classification part is filled in at least one of the pale color layers to indicate a classification of the game token money. The classification part is recognizable from a side face and a front face of the game token money. The RFID contains information regarding a value of the game token money and a classification of the game token money indicated by the classification part.

    DOUBLE CHIP TRAY, CHIP TRAY, AND GAME MANAGEMENT SYSTEM

    公开(公告)号:US20230360470A1

    公开(公告)日:2023-11-09

    申请号:US18218835

    申请日:2023-07-06

    发明人: Yasushi SHIGETA

    IPC分类号: G07F17/32 G06K19/04

    摘要: There is provided a game management system that can manage games using RFID tags built into chips even when multiple types of chips are housed in a chip tray, and a double chip tray used for the system. A chip tray is a double chip tray equipped with a chip tray reader capable of reading two types of chips of different shapes and/or sizes that incorporate RFID tags, namely round chips and plaque chips, an upper chip holder that can hold chips, and a lower chip holder that can hold chips. The chip tray reader is configured to read the RFID tags of the two types of chips held in the chip tray, and is capable of determining the respective amounts.