公开(公告)号：US20060028277A1

公开(公告)日：2006-02-09

申请号：US11247185

申请日：2005-10-12

Applicant: Kiichi Yamashita ,  Tomonori Tanoue ,  Shizuo Kondo

Inventor： Kiichi Yamashita ,  Tomonori Tanoue ,  Shizuo Kondo

IPC: H03G3/10

CPC classification number: H03F1/02 ,  H03F1/30 ,  H03F3/21 ,  H03G7/001 ,  H03G7/06

Abstract: The present invention provides a power amplifier module featuring that: its output power characteristic smoothly changes as the input control Voltage changes; and its control sensitivity is stable over a wide dynamic range. By same means, idling current for gain setting is supplied to a single amplifier element or all of multiple stages of amplifier elements of the power amplifier module. By making this idling current behave so as to exponentially change, relative to input control voltage, the invention enables output power control proportional to the input control voltage.

Abstract translation: 本发明提供了一种功率放大器模块，其特征在于：其输出功率特性随着输入控制电压的变化而平滑地变化; 其控制灵敏度在宽动态范围内稳定。 通过同样的方式，用于增益设定的空载电流被提供给功率放大器模块的单个放大器元件或放大器元件的多个级的全部。 通过使该怠速电流相对于输入控制电压发生指数变化，本发明实现与输入控制电压成比例的输出功率控制。

公开(公告)号：US06984871B2

公开(公告)日：2006-01-10

申请号：US10441096

申请日：2003-05-20

Applicant: Tomonori Tanoue ,  Kazuhiro Mochizuki ,  Hiroji Yamada

Inventor： Tomonori Tanoue ,  Kazuhiro Mochizuki ,  Hiroji Yamada

IPC: H01L27/082

CPC classification number: H01L29/66318 ,  H01L24/32 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/41708 ,  H01L29/7371 ,  H01L2924/1305 ,  H01L2924/15787 ,  H01L2924/00

Abstract: A semiconductor device with high structural reliability and low parasitic capacitance is provided. In one example, the semiconductor device has a surface. The semiconductor device comprises a semiconductor region, wherein an emitter region, a base region, and a collector region are laminated from a side near a substrate of the semiconductor region; an insulating protection layer disposed on the surface; and a wiring layer disposed on the surface, the insulating protection layer forming a via hole from the side of the substrate of the semiconductor region, the via hole being formed to allow the wiring layer to make a contact to an electrode of the emitter region from a side of the substrate where the emitter region, the base region, and the collector region are laminated and where the semiconductor region is isolated.

Abstract translation: 提供具有高结构可靠性和低寄生电容的半导体器件。 在一个示例中，半导体器件具有表面。 半导体器件包括半导体区域，其中从半导体区域的衬底附近的一侧层叠发射极区域，基极区域和集电极区域; 设置在所述表面上的绝缘保护层; 以及设置在所述表面上的布线层，所述绝缘保护层从所述半导体区域的所述基板的侧面形成通孔，所述通孔形成为允许所述布线层与所述发射极区域的电极接触 衬底的一侧，其中发射极区域，基极区域和集电极区域被层叠并且半导体区域被隔离。

公开(公告)号：US06816017B2

公开(公告)日：2004-11-09

申请号：US09931877

申请日：2001-08-20

Applicant: Kiichi Yamashita ,  Tomonori Tanoue ,  Isao Ohbu ,  Kenji Sekine

Inventor： Kiichi Yamashita ,  Tomonori Tanoue ,  Isao Ohbu ,  Kenji Sekine

IPC: H03F152

CPC classification number: H03F3/19 ,  H03F1/0261 ,  H03F1/302 ,  H03F3/347 ,  H03F2200/444

Abstract: A power amplifier module is provided with a function of protecting an amplifying device against destruction caused by a standing wave by reflection from an antenna end in load variation. Increase in base current from idling current of a final stage amplifying portion GaAs-HBT in load variation is detected and canceled and collector current is restrained to thereby prevent an increase in output and prevent destruction of GaAs-RET. By also using a function of successively lowering idling current when power source voltage is elevated and a clipping function of diodes connected in parallel with output stage GaAs-RET, voltage as well as current more than necessary are avoided from being applied on the output stage GaAs-RET.

Abstract translation: 功率放大器模块具有保护放大装置的功能，以防止由负载变化引起的天线反射引起的驻波的破坏。 检测并抵消了负载变化中的最终级放大部分GaAs-HBT的空载电流的基极电流的增加，并抑制集电极电流，从而防止输出增加并防止GaAs-RET的破坏。 通过使用在电源电压升高时连续降低空载电流并且与输出级GaAs-RET并联连接的二极管的限幅功能也被避免施加在输出级GaAs上的功能。 -RET。

公开(公告)号：US5481120A

公开(公告)日：1996-01-02

申请号：US164801

申请日：1993-12-10

Applicant: Kazuhiro Mochizuki ,  Tomoyoshi Mishima ,  Tohru Nakamura ,  Hiroshi Masuda ,  Tomonori Tanoue ,  Tooru Haga ,  Yoshihisa Fujisaki

Inventor： Kazuhiro Mochizuki ,  Tomoyoshi Mishima ,  Tohru Nakamura ,  Hiroshi Masuda ,  Tomonori Tanoue ,  Tooru Haga ,  Yoshihisa Fujisaki

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/20 ,  H01L29/45 ,  H01L29/737 ,  H01L29/80 ,  H01S5/042 ,  H01S5/183 ,  H01S5/22 ,  H01S5/323 ,  H01L27/02

CPC classification number: H01S5/18347 ,  H01L29/0891 ,  H01L29/20 ,  H01L29/452 ,  H01L29/66318 ,  H01L29/7371 ,  H01S5/0424 ,  H01L29/802 ,  H01S2304/02 ,  H01S5/18341 ,  H01S5/18369 ,  H01S5/32316

Abstract: Disclosed is a semiconductor device using a polycrystalline compound semiconductor with a low resistance as a low resistance layer, and its fabrication method. The above polycrystalline compound semiconductor layer is doped with C or Be as impurities in a large amount, and is extremely low in resistance. The polycrystalline compound semiconductor layer is formed by either of a molecular beam epitaxy method, an organometallic vapor phase epitaxy method and an organometallic molecular beam epitaxy method under the condition that a substrate temperature is 450.degree. C. or less and the ratio of partial pressure of a V-group element to a III-group element is 50 or more. In the case that the above polycrystaline compound semiconductor layer with a low resistance is used as an extrinsic base region of an heterojunction bipolar transistor, since the extrinsic base region can be formed on a dielectric film formed on a collector, it is possible to reduce the base-collector capacitance, and hence to enhance the operational speed of the heterojunction bipolar transistor.

Abstract translation: 公开了使用具有低电阻的多晶化合物半导体作为低电阻层的半导体器件及其制造方法。 上述多晶化合物半导体层以C或Be作为杂质被大量掺杂，并且电阻极低。 多晶化合物半导体层通过分子束外延法，有机金属气相外延法和有机金属分子束外延法中的任一种形成，在基板温度为450℃以下的条件下， 对于III族元素的V族元素为50以上。 在上述具有低电阻的多晶化合物半导体层用作异质结双极晶体管的外在基极区域的情况下，由于可以在形成在集电体上的电介质膜上形成非本征基区，因此可以减少 基极集电极电容，从而提高异质结双极晶体管的工作速度。

公开(公告)号：US5381027A

公开(公告)日：1995-01-10

申请号：US134622

申请日：1993-10-12

Applicant: Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

Inventor： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

IPC: H01L21/18 ,  H01L21/285 ,  H01L21/331 ,  H01L21/335 ,  H01L27/06 ,  H01L29/737 ,  H01L29/778 ,  H01L29/804 ,  H01L29/784

CPC classification number: H01L29/66318 ,  H01L21/182 ,  H01L21/28587 ,  H01L27/0605 ,  H01L29/66462 ,  H01L29/7373 ,  H01L29/7787

Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.

Abstract translation: 本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。 前者通过应用于其源极和漏极区域的形成来制造通过诸如通过离子注入引起杂质的异质结的紊乱或通过形成由 选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。 后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。 这些半导体器件可以降低源极栅极电阻和寄生基极电阻。 本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

公开(公告)号：US5019524A

公开(公告)日：1991-05-28

申请号：US401506

申请日：1989-08-30

Applicant: Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushiro Kusano ,  Masayoshi Kobayashi ,  Susumu Takahashi

Inventor： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushiro Kusano ,  Masayoshi Kobayashi ,  Susumu Takahashi

IPC: H01L29/205 ,  H01L21/331 ,  H01L29/10 ,  H01L29/73 ,  H01L29/737

CPC classification number: H01L29/66318 ,  H01L29/1004 ,  H01L29/7371 ,  Y10S148/01 ,  Y10S148/072 ,  Y10S148/084

Abstract: Disclosed is a semiconductor device including a heterojunction bipolar transistor in which the front surface of a base layer and the surface of an emitter-base junction are covered with a high-resistivity layer of compound semiconductor containing at least one constituent element common to an emitter layer and the base layer.

公开(公告)号：US5017973A

公开(公告)日：1991-05-21

申请号：US287738

申请日：1988-12-21

Applicant: Hiroshi Mizuta ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

Inventor： Hiroshi Mizuta ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

IPC: H01L29/15 ,  H01L29/201 ,  H01L29/205 ,  H01L29/68 ,  H01L29/88

CPC classification number: B82Y10/00 ,  H01L29/155 ,  H01L29/882

Abstract: A resonant tunneling device includes a superlattice layer which includes an interlaminated structure of three semiconductor layers each having a narrow energy bandgap and serving as a quantum well layer and four semiconductor layers each having a wide energy bandgap and serving as a barrier layer and in which three quantum levels are formed in the quantum well layers. A resonant tunneling phenomenon produced between the quantum levels provides peak current values which are substantially equal to each other, peak voltages which can be set independently from each other, and peak-to-valley (P/V) ratios which are high, thereby realizing a resonant tunneling device which has an excellent performance as a three state logic element for a logic circuit. By increasing the number of quantum well layers and the number of barrier layers, a logic element of four or more states can be realized for a logic circuit.

公开(公告)号：US4979009A

公开(公告)日：1990-12-18

申请号：US415708

申请日：1989-09-29

Applicant: Chushiro Kusano ,  Tomonori Tanoue ,  Katsuhiko Mitani

Inventor： Chushiro Kusano ,  Tomonori Tanoue ,  Katsuhiko Mitani

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737

CPC classification number: H01L29/7371

Abstract: 2A heterojunction bipolar transistor is disclosed in which a region of a base layer which extends in the vicinity of the interface between the base layer and an emitter layer is doped with an impurity at a higher concentration than that in the inside of the base layer to thereby form a built-in field by which carriers injected from the emitter are caused to drift to the inside of the base layer. In the transistor having this structure, the current gain does not depend on the emitter area, and it is possible to obtain a large current gain with a small emitter area.

Abstract translation: 2A公开了其中在基极层和发射极层之间的界面附近延伸的基极层的区域以比基底层内侧的浓度更高的浓度掺杂杂质的异质结双极晶体管，由此 形成内置的场，通过该场，使从发射器注入的载流子漂移到基层的内部。 在具有这种结构的晶体管中，电流增益不取决于发射极面积，并且可以获得具有小发射极面积的大电流增益。