公开(公告)号：US20170255575A1

公开(公告)日：2017-09-07

申请号：US15233850

申请日：2016-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G06F13/42

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20170242822A1

公开(公告)日：2017-08-24

申请号：US15136775

申请日：2016-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG

IPC: G06F15/173 ,  H04L29/08 ,  G06F1/30 ,  G06F3/06

CPC classification number: G06F15/17331 ,  G06F1/30 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0685 ,  H04L67/1095 ,  H04L67/1097 ,  H04L69/16

Abstract: A memory device includes: a plurality of volatile memories for storing data; a non-volatile memory buffer configured to store data associated with workloads received from a host computer; and a memory controller configured to store the data to both the plurality of volatile memories and the non-volatile memory buffer and replicate the data to a remote node. The non-volatile memory buffer is configured to store the data in a table including an acknowledgement bit that is set by the remote node.

公开(公告)号：US20170242595A1

公开(公告)日：2017-08-24

申请号：US15136872

申请日：2016-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG

IPC: G06F3/06 ,  G06F12/10 ,  G11C13/00

CPC classification number: G06F3/0613 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/1028 ,  G11C8/06 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  Y02D10/13

Abstract: A non-volatile memory comprises an array of a plurality of non-volatile memory cells, a controller coupled to the array, and an evaluator coupled to an output of the array. In a first operational mode, the controller receives a logical address and selects one non-volatile memory cell for access. In a second operational mode, and the controller receives a logical address and selects N non-volatile memory cells for access in which N is an integer greater than 1. If the logical address is for a read access, in the first operational mode the evaluator is disabled and the read-address output of the array corresponds to one selected non-volatile memory cell, and in the second operational mode the evaluator determines an read-address output corresponding to the received logical address based on a read output of the N selected non-volatile memory cells.

公开(公告)号：US20170192686A1

公开(公告)日：2017-07-06

申请号：US15017391

申请日：2016-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0631 ,  G06F3/0641 ,  G06F3/0644 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/1041 ,  G06F2212/205 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/7208

Abstract: A hybrid module includes one or more memory modules, each of which includes one or more memory devices and a memory controller, one or more storage modules, each of which includes one or more storage devices and a storage controller. A host interface of the hybrid module includes a main controller and provides an interface with the memory controller and the storage controller. A transaction-based memory interface provides an interface between the main controller and a host memory controller.

公开(公告)号：US20170060788A1

公开(公告)日：2017-03-02

申请号：US14959773

申请日：2015-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien CHANG ,  Hongzhong ZHENG ,  Liang YIN

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/4068

Abstract: A memory system includes a master controller, an interface with a host computer, and a link bus configured to couple with a slave controller. The master controller includes an address mapping decoder, a transaction queue, and a scheduler. The address mapping decoder is configured to decode address mapping information of a memory device coupled to the slave controller. The scheduler of the master controller is configured to reorder memory transaction requests received from the host computer in the transaction queue using the address mapping information of the memory device. The memory system employs an extended open page policy based on the pending memory transaction requests in the transaction queue of the master controller.

Abstract translation: 存储器系统包括主控制器，与主计算机的接口以及被配置为与从属控制器耦合的链路总线。 主控制器包括地址映射解码器，事务队列和调度器。 地址映射解码器被配置为解码耦合到从控制器的存储器件的地址映射信息。 主控制器的调度器被配置为使用存储器设备的地址映射信息来重新排序从事务队列中的主计算机接收的存储器事务请求。 存储器系统基于主控制器的事务队列中的待处理存储器事务请求采用扩展的打开页面策略。

公开(公告)号：US20170040050A1

公开(公告)日：2017-02-09

申请号：US15299445

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mu-Tien CHANG ,  Krishna MALLADI ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C5/04 ,  G11C11/40618 ,  G11C11/4076

Abstract: A memory (1205) is disclosed. The memory (1205) can includes a stack of dynamic Random Access Memory (DRAM) cores (1210, 1215, 1220, 1225) in a three-dimensional stacked memory architecture (1230). Each of the DRAM cores (1210, 1215, 1220, 1225) can include a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data. The memory (1205) can also include logic layer (1235) which can include an interface (1305) to connect the memory (1205) with a processor (120). The logic layer (1235) can also include a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4) and a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

Abstract translation: 公开了一种存储器（1205）。 存储器（1205）可以包括三维堆叠存储器架构（1230）中的动态随机存取存储器（DRAM）核心（1210,1215,1220,1225）堆叠。 每个DRAM内核（1210,1215,1220,1225）可以包括用于存储数据的多个存储体（205-1,205-2,205-3,205-4）。 存储器（1205）还可以包括逻辑层（1235），其可以包括将存储器（1205）与处理器（120）连接的接口（1305）。 逻辑层（1235）还可以包括刷新引擎（115），其可用于刷新多个存储体（205-1,205-2,205-3,205-4）中的一个和一个智能刷新组件（ 305），其可以建议刷新引擎（115）哪个存储体使用无序刷新每次刷新刷新。 在刷新时，智能刷新组件（305）可以使用逻辑（415）来识别事务队列（430）中的待处理事务中的最远存储体。