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    Methods of forming transistor devices and capacitor constructions
    61.
    发明授权
    Methods of forming transistor devices and capacitor constructions 有权
    形成晶体管器件和电容器结构的方法

    公开(公告)号：US07253053B2

    公开(公告)日：2007-08-07

    申请号：US10757253

    申请日：2004-01-13

    Applicant: Denise M. Eppich ,  Ronald A. Weimer

    Inventor： Denise M. Eppich ,  Ronald A. Weimer

    IPC: H01L21/8242

    CPC classification number: H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28167 ,  H01L21/28202 ,  H01L27/0629 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/84 ,  H01L28/90 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    Abstract: The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 Å (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and a dielectric layer. The conductively-doped silicon can be n-type silicon and the dielectric layer can be a high-k dielectric material. The metal-containing material can be formed directly on the dielectric layer, and the conductively-doped silicon can be formed directly on the metal-containing material. The circuit device can be a capacitor construction or a transistor construction. If the circuit device is a transistor construction, such can be incorporated into a CMOS assembly. Various devices of the present invention can be incorporated into memory constructions, and can be incorporated into electronic systems.

    Abstract translation: 本发明包括形成电路装置的方法。 在导电掺杂的硅和电介质层之间形成包含不大于（或者包括不超过70个ALD循环的厚度）的厚度的含金属材料。 导电掺杂的硅可以是n型硅，并且介电层可以是高k电介质材料。 含金属材料可以直接形成在电介质层上，并且导电掺杂的硅可以直接形成在含金属的材料上。 电路器件可以是电容器结构或晶体管结构。 如果电路器件是晶体管结构，则可以将其并入CMOS组件中。 本发明的各种装置可以结合到存储器结构中，并且可以并入到电子系统中。

    Method of composite gate formation
    62.
    发明授权
    Method of composite gate formation 有权
    复合栅极形成方法

    公开(公告)号：US07247920B2

    公开(公告)日：2007-07-24

    申请号：US10931840

    申请日：2004-09-01

    Applicant: Ronald A. Weimer

    Inventor： Ronald A. Weimer

    IPC: H01L29/76

    CPC classification number: H01L21/28185 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

    Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.

    Abstract translation: 提供了在诸如栅极结构和势垒层，半导体器件和栅电极的半导体器件中形成氮化物阻挡膜层的方法。 氮化物层特别可用作硼扩散到氧化膜中的阻挡层。 氮化物阻挡层通过将硅选择性地沉积到氧化物衬底上作为薄层而形成，然后对含氮物质中的硅层进行热退火或将硅暴露于等离子体氮源以使硅层氮化。

    Method of improved high K dielectric—polysilicon interface for CMOS devices
    63.
    发明授权
    Method of improved high K dielectric—polysilicon interface for CMOS devices 有权
    用于CMOS器件的改进的高K介质 - 多晶硅接口的方法

    公开(公告)号：US07227209B2

    公开(公告)日：2007-06-05

    申请号：US10280387

    申请日：2002-10-25

    Applicant: Ronald A. Weimer

    Inventor： Ronald A. Weimer

    IPC: H01L29/94

    CPC classification number: H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/84

    Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon. The nitridized oxynitride layer inhibits oxidation of the underlying polysilicon layer in a post-treatment oxidizing anneal of the high K dielectric, thus maintaining the oxide layer as a thin layer over the polysilicon layer.

    Abstract translation: 提供了在多晶硅衬底上形成电介质层的方法，其用于构建电容器和其它半导体电路部件。 利用多晶硅层（例如HSG多晶硅电容器电极）在小于800℃下的自限制性一氧化氮（NO）退火，以在多晶硅上生长约40埃或更少的薄氧化物（氧氮化物）层 层。 NO退火在多晶硅 - 氧化物界面处提供氮层，限制多晶硅层的进一步氧化和氧化物层的生长。 将氧化物层暴露于含氮气体中以氮化氧化物层的表面并降低氧化物层的有效介电常数。 该方法特别适用于在多晶硅上形成高K电介质绝缘层，例如五氧化二钽。 氮化氮氧化物层在高K电介质的后处理氧化退火中抑制下面的多晶硅层的氧化，从而将氧化物层保持在多晶硅层上的薄层。

    Method of improved high K dielectric-polysilicon interface for CMOS devices
    65.
    发明授权
    Method of improved high K dielectric-polysilicon interface for CMOS devices 有权

    公开(公告)号：US07129128B2

    公开(公告)日：2006-10-31

    申请号：US09941827

    申请日：2001-08-29

    Applicant: Ronald A. Weimer

    Inventor： Ronald A. Weimer

    IPC: H01L21/8242

    CPC classification number: H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/84

    Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon. The nitridized oxynitride layer inhibits oxidation of the underlying polysilicon layer in a post-treatment oxidizing anneal of the high K dielectric, thus maintaining the oxide layer as a thin layer over the polysilicon layer.

    Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source
    67.
    发明授权
    Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source 有权
    制造具有暴露于含氢氮源的电介质层的集成电路的方法

    公开(公告)号：US06924197B2

    公开(公告)日：2005-08-02

    申请号：US10378568

    申请日：2003-03-03

    Applicant: Ronald A. Weimer

    Inventor： Ronald A. Weimer

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/792 ,  Y10T29/41

    Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

    Abstract translation: 本发明提供一种闪速存储器集成电路及其制造方法。 在可擦除可编程只读存储器（EPROM）器件中的隧道电介质被含氢化合物，特别是氨氮化。 因此，氢与氮一起并入隧道电介质中。 蚀刻并完成了栅极堆叠，包括保护性侧壁间隔物和电介质盖，并且叠置有对羟基和氢物质的屏障。 尽管衬垫有利地将杂质扩散减少到隧道电介质和衬底界面，但是在任何随后的氢退火中也可以减少氢扩散。 然而，在先前暴露于氨中时，向隧道电介质提供氢。

    Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source
    68.
    发明授权
    Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source 失效
    制造具有暴露于含氢氮源的电介质层的集成电路的方法

    公开(公告)号：US06815805B2

    公开(公告)日：2004-11-09

    申请号：US10758518

    申请日：2004-01-15

    Applicant: Ronald A. Weimer

    Inventor： Ronald A. Weimer

    IPC: H01L2358

    CPC classification number: H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/792 ,  Y10T29/41

    Abstract: The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only memory (EPROM) device is nitrided with a hydrogen-bearing compound, particularly ammonia. Hydrogen is thus incorporated into the tunnel dielectric, along with nitrogen. The gate stack is etched and completed, including protective sidewall spacers and dielectric cap, and the stack lined with a barrier to hydroxyl and hydrogen species. Though the liner advantageously reduces impurity diffusion through to the tunnel dielectric and substrate interface, it also reduces hydrogen diffusion in any subsequent hydrogen anneal. Hydrogen is provided to the tunnel dielectric, however, in the prior exposure to ammonia.

    Abstract translation: 本发明提供一种闪速存储器集成电路及其制造方法。 在可擦除可编程只读存储器（EPROM）器件中的隧道电介质被含氢化合物，特别是氨氮化。 因此，氢与氮一起并入隧道电介质中。 蚀刻并完成了栅极堆叠，包括保护性侧壁间隔物和电介质盖，并且叠置有对羟基和氢物质的屏障。 尽管衬垫有利地将杂质扩散减少到隧道电介质和衬底界面，但是在任何随后的氢退火中也可以减少氢扩散。 然而，在先前暴露于氨中时，向隧道电介质提供氢。

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