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61.
公开(公告)号:US10417069B2
公开(公告)日:2019-09-17
申请号:US15829701
申请日:2017-12-01
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Clint A. Hardy , Matthew G. Borlick , Adrian C. Gerhard , Lokesh M. Gupta
Abstract: Provided are a computer program product, system, and method for managing I/O requests to a storage array of storage devices in a machine having a processor node and device adaptor. In response to initiating a rebuild of data in the storage array, the device adaptor determines whether a remaining fault tolerance at the storage array comprises a non-zero fault tolerance that permits at least one further storage device to fail and still allow recovery of data stored in the storage array. In response to determining that the remaining fault tolerance is a zero fault tolerance that does not permit at least one storage device to fail and allow recovery of data, the device adaptor sends a message to the processor node to cause the processor node to initiate an emergency protocol to terminate a mission critical operation when the processor node is performing the mission critical operation.
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公开(公告)号:US10372368B2
公开(公告)日:2019-08-06
申请号:US15292202
申请日:2016-10-13
Applicant: International Business Machines Corporation
Inventor: Robert Galbraith , Adrian C. Gerhard , Daniel F. Moertl
Abstract: Operating a RAID array with unequal stripes, the RAID array comprising N number of drives, where each RAID stripe includes P number of parity drives and N-P number of data drives, including buffering, by a RAID controller, write operations received from a host, each write operation specifying data to be written to the RAID array; distributing, by the RAID controller, the data to be written amongst N-P write groups, including: dividing the data into chunks of a sub-stripe size, wherein the sub-stripe size is less than a parity stripe size; and assigning the chunks, in round-robin order, to the N-P write groups; calculating parity from the N-P write groups; and writing the N-P write groups and the calculated parity as a first RAID stripe to the RAID array.
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公开(公告)号:US10261907B2
公开(公告)日:2019-04-16
申请号:US15454389
申请日:2017-03-09
Applicant: International Business Machines Corporation
Inventor: Robert Galbraith , Adrian C. Gerhard , Daniel F. Moertl
IPC: G06F12/08 , G06F12/0868 , G06F12/0875 , G06F12/0873 , G06F12/0871
Abstract: Caching data in a redundant array of independent disks (RAID) storage system including receiving an operation instruction targeting a location in an attached memory of the RAID storage system, wherein the attached memory temporarily stores data for storage on RAID storage devices, and wherein the operation instruction is one selected from a group consisting of a read instruction and a write instruction; redirecting, based on a content of the operation instruction, the operation instruction from the attached memory to the embedded memory on the RAID storage system; and servicing the operation instruction by accessing a portion of the embedded memory corresponding to the location in the attached memory of the RAID storage system.
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公开(公告)号:US10067880B2
公开(公告)日:2018-09-04
申请号:US15055770
申请日:2016-02-29
Applicant: International Business Machines Corporation
Inventor: Joseph R. Edwards , Robert Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Gowrisankar Radhakrishnan , Rick A. Weckwerth
IPC: G06F12/00 , G06F12/1009 , G06F3/06
Abstract: Disclosed are embodiments for supporting dynamic tier remapping of data stored in a hybrid storage system. One embodiment includes a storage controller and firmware, where the firmware maintains a plurality of mapping elements, where each mapping element includes a plurality of group identifiers, where each group identifier is configured to indicate a mapping of a logical block addresses, and where the storage controller performs: receiving a read command including a logical block address; parsing the logical block address to determine a mapping element and a group identifier; determining, for a particular mapping element of the plurality of elements, whether the particular mapping element is locked, wherein the particular mapping element corresponds to the mapping element of the logical block address; and dependent upon the particular mapping element, queuing the read command for firmware processing or remapping the logical block address.
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65.
公开(公告)号:US10055573B2
公开(公告)日:2018-08-21
申请号:US15810021
申请日:2017-11-11
Applicant: International Business Machines Corporation
Inventor: Brian E. Bakke , Adrian C. Gerhard , Daniel F. Moertl
CPC classification number: G06F21/45 , G06F9/45558 , G06F21/44 , G06F21/604 , G06F21/606 , G06F21/6218 , G06F21/85 , G06F2009/45579 , G06F2221/2141 , H04L63/101
Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization and deauthorization processing for a Coherent Accelerator Processor Interface (CAPI) adapter. The Application Client, such as an Application Child Client sends a Delete Authorizations command to the CAPI Adapter via the Client CAPI Server Registers assigned to the specific Application Client. The CAPI Adapter deletes the Authorizations in all Lists in the Delete Authorizations command.
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公开(公告)号:US10013572B2
公开(公告)日:2018-07-03
申请号:US15811553
申请日:2017-11-13
Applicant: International Business Machines Corporation
Inventor: Brian E. Bakke , Adrian C. Gerhard , Daniel F. Moertl
CPC classification number: G06F3/062 , G06F3/0637 , G06F3/064 , G06F3/0659 , G06F3/0673 , G06F9/45558 , G06F12/1425 , G06F13/382 , G06F21/53 , G06F21/604 , G06F21/6218 , G06F2009/45579 , G06F2009/45583 , G06F2212/1052 , G06F2221/2141
Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization command flow processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client builds a command including start LBA and number of LBAs and Child Authorization Handle. The Application Client sends the command directly to the CAPI Adapter via the Application Clients CAPI Server Registers assigned to the specific Application Client. The CAPI adapter validate that the requesting Client is authorized to perform the command using the Authorization Handle and the receiving CAPI Server Register address. The CAPI Adapter executes the validated command and sends completion back to the Application Client.
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公开(公告)号:US09940258B2
公开(公告)日:2018-04-10
申请号:US14940050
申请日:2015-11-12
Applicant: International Business Machines Corporation
Inventor: Brian E. Bakke , Joseph R. Edwards , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Gowrisankar Radhakrishnan , Rick A. Weckwerth
IPC: G06F12/0895 , G06F12/122 , G06F12/0868 , G06F12/0891 , G06F12/0893 , G06F13/40 , G06F13/42 , G06F13/28
CPC classification number: G06F12/0895 , G06F3/0619 , G06F3/065 , G06F3/0665 , G06F3/0689 , G06F12/0806 , G06F12/0868 , G06F12/0891 , G06F12/0893 , G06F12/12 , G06F12/122 , G06F12/123 , G06F12/128 , G06F13/28 , G06F13/4022 , G06F13/4282 , G06F2212/222 , G06F2212/604 , G06F2212/6042 , G06F2212/621 , G06F2212/69
Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages merging data with existing data on fast writes to storage write cache substantially without using firmware for greatly enhancing performance.
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公开(公告)号:US09940255B2
公开(公告)日:2018-04-10
申请号:US14939961
申请日:2015-11-12
Applicant: International Business Machines Corporation
Inventor: Brian E. Bakke , Joseph R. Edwards , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Gowrisankar Radhakrishnan , Rick A. Weckwerth
IPC: G06F12/0895 , G06F12/122 , G06F12/0868 , G06F12/0891 , G06F12/0893 , G06F13/40 , G06F13/42 , G06F13/28
CPC classification number: G06F12/0895 , G06F3/0619 , G06F3/065 , G06F3/0665 , G06F3/0689 , G06F12/0806 , G06F12/0868 , G06F12/0891 , G06F12/0893 , G06F12/12 , G06F12/122 , G06F12/123 , G06F12/128 , G06F13/28 , G06F13/4022 , G06F13/4282 , G06F2212/222 , G06F2212/604 , G06F2212/6042 , G06F2212/621 , G06F2212/69
Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs data age identification in storage write cache substantially without firmware involvement for greatly enhancing performance.
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69.
公开(公告)号:US20180075232A1
公开(公告)日:2018-03-15
申请号:US15810021
申请日:2017-11-11
Applicant: International Business Machines Corporation
Inventor: Brian E. Bakke , Adrian C. Gerhard , Daniel F. Moertl
CPC classification number: G06F21/45 , G06F9/45558 , G06F21/44 , G06F21/604 , G06F21/606 , G06F21/6218 , G06F21/85 , G06F2009/45579 , G06F2221/2141 , H04L63/101
Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization and deauthorization processing for a Coherent Accelerator Processor Interface (CAPI) adapter. The Application Client, such as an Application Child Client sends a Delete Authorizations command to the CAPI Adapter via the Client CAPI Server Registers assigned to the specific Application Client. The CAPI Adapter deletes the Authorizations in all Lists in the Delete Authorizations command.
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公开(公告)号:US20180068129A1
公开(公告)日:2018-03-08
申请号:US15811553
申请日:2017-11-13
Applicant: International Business Machines Corporation
Inventor: Brian E. Bakke , Adrian C. Gerhard , Daniel F. Moertl
CPC classification number: G06F3/062 , G06F3/0637 , G06F3/064 , G06F3/0659 , G06F3/0673 , G06F9/45558 , G06F12/1425 , G06F13/382 , G06F21/53 , G06F21/604 , G06F21/6218 , G06F2009/45579 , G06F2009/45583 , G06F2212/1052 , G06F2221/2141
Abstract: A method, system and computer program product are provided for implementing block extent granularity authorization command flow processing for a Coherent Accelerator Processor Interface (CAPI) adapter. An Application Client builds a command including start LBA and number of LBAs and Child Authorization Handle. The Application Client sends the command directly to the CAPI Adapter via the Application Clients CAPI Server Registers assigned to the specific Application Client. The CAPI adapter validate that the requesting Client is authorized to perform the command using the Authorization Handle and the receiving CAPI Server Register address. The CAPI Adapter executes the validated command and sends completion back to the Application Client.
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