公开(公告)号：US06441423B1

公开(公告)日：2002-08-27

申请号：US09584357

申请日：2000-05-31

申请人： Jack A. Mandelman ,  Rama Divakaruni

发明人： Jack A. Mandelman ,  Rama Divakaruni

IPC分类号： H01L27108

CPC分类号： H01L27/10861

摘要： The preferred embodiment of the present invention provides an improved capacitor design that overcomes many of the limitations of the prior art. The preferred embodiment of the present invention uses germanium to adjust the work function of the storage node. Specifically, the addition of germanium modifies the fermi level of the storage node, moving the fermi level towards the conduction band. This modification of the fermi level reduces the difference in conduction band-edge potentials between the storage node and the counter electrode, thus reducing the maximum electric potential seen across the capacitor. In the preferred embodiment, p-type doped silicon germanium is formed in the trench capacitor adjacent to the capacitor dielectric layer. A barrier layer is then formed over the doped silicon germanium, and the remaining storage node area is filled with n+-type polysilicon. The p-type doped silicon germanium adjusts the workfunction of the capacitor storage node, moving the fermi level toward the conduction band. This minimizes the maximum difference between conduction band-edge potentials of the storage node and the buried plate, which serves as the counter electrode. This has the effect of balancing the electric potential seen across the dielectric for stored high and stored low situations. This reduces the maximum electric potential seen across the capacitor dielectric. This solution improves the reliability of the capacitor, especially those capacitors with relatively thin dielectric layers, without requiring additional circuitry to bias the buried plate, and without increasing power consumption. The preferred embodiment also reduces leakage current through the capacitor dielectric, thus increasing signal retention time.

摘要翻译： 本发明的优选实施例提供了一种改进的电容器设计，其克服了现有技术的许多限制。 本发明的优选实施例使用锗来调节存储节点的功能。 具体地说，锗的添加改变存储节点的费米能级，将费米能级移向导带。 费米能级的这种修改降低了存储节点和对电极之间的导带边缘电位的差异，从而减少了跨越电容器的最大电位。 在优选实施例中，在与电容器介电层相邻的沟槽电容器中形成p型掺杂硅锗。 然后在掺杂的硅锗上形成阻挡层，并且剩余的存储节点区域填充有n +型多晶硅。 p型掺杂硅锗调节电容器存储节点的功函数，将费米电平移向导带。 这使存储节点的导带边缘电位与用作对电极的掩埋板之间的最大差异最小化。 这具有平衡在存储的高和存储的低情况下跨过电介质看到的电位的效果。 这降低了在电容器电介质两端看到的最大电位。 该解决方案提高了电容器的可靠性，特别是具有相对薄的介电层的电容器，而不需要额外的电路来偏置掩埋板，并且不增加功耗。 优选实施例还减少了通过电容器电介质的泄漏电流，从而增加了信号保持时间。

公开(公告)号：US06373086B1

公开(公告)日：2002-04-16

申请号：US09607135

申请日：2000-06-29

申请人： Jack A. Mandelman ,  Rama Divakaruni ,  Byeong Y. Kim

发明人： Jack A. Mandelman ,  Rama Divakaruni ,  Byeong Y. Kim

IPC分类号： H01L27108

CPC分类号： H01L27/10867 ,  H01L27/1087 ,  H01L29/945

摘要： A deep trench capacitor having a modified sidewall geometry within the collar isolation region such that the threshold voltage of the vertical parasitic MOSFET between a buried-strap out-diffusion and a N+ capacitor plate is significantly increased as compared to a conventional arrangement. By forming a concave notch within the sidewalls of the capacitor, the electrical thickness of the gate dielectric is effectively thicker than its actual physical thickness. Thereby, a reduced amount of gate dielectric and dopant is needed for suppression of vertical parasitic MOSFET conduction.

摘要翻译： 一种深沟槽电容器，其具有在套环隔离区域内的改进的侧壁几何形状，使得与常规布置相比，掩埋带外扩散与N +电容器板之间的垂直寄生MOSFET的阈值电压显着增加。 通过在电容器的侧壁内形成凹陷痕，栅极电介质的电气厚度比其实际物理厚度有效厚。 因此，需要减少量的栅极电介质和掺杂剂来抑制垂直寄生MOSFET导通。

公开(公告)号：US06348394B1

公开(公告)日：2002-02-19

申请号：US09573375

申请日：2000-05-18

申请人： Jack A. Mandelman ,  Rama Divakaruni ,  Herbert Ho ,  Giuseppe La Rosa ,  Yujun Li ,  Jochen Beintner ,  Radhika Srinivasan

发明人： Jack A. Mandelman ,  Rama Divakaruni ,  Herbert Ho ,  Giuseppe La Rosa ,  Yujun Li ,  Jochen Beintner ,  Radhika Srinivasan

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224

摘要： A semiconductor device and method of manufacturing thereof are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. A nitride liner is formed in the trench. Charge is trapped in the nitride liner. In a preferred embodiment, the trench is filled with an oxide by an HDP process to increase the amount of charge trapped in the nitride liner. Preferably, the oxide fill is formed directly on the nitride liner.

摘要翻译： 提供半导体器件及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 氮化物衬垫形成在沟槽中。 电荷被困在氮化物衬垫中。 在优选实施例中，沟槽通过HDP工艺填充氧化物以增加在氮化物衬垫中捕获的电荷量。 优选地，氧化物填充物直接形成在氮化物衬垫上。

公开(公告)号：US06340615B1

公开(公告)日：2002-01-22

申请号：US09466605

申请日：1999-12-17

申请人： Sundar K. Iyer ,  Rama Divakaruni ,  Herbert L. Ho ,  Subramanian Iyer ,  Babar A. Khan

发明人： Sundar K. Iyer ,  Rama Divakaruni ,  Herbert L. Ho ,  Subramanian Iyer ,  Babar A. Khan

IPC分类号： H01L218242

CPC分类号： H01L27/10867

摘要： A method of connecting a trench capacitor in a dynamic random access memory (DRAM) cell. First, trenches are formed in a silicon substrate using a masking layer including a pad nitride layer on a pad oxide layer. Trench capacitors are formed in the trenches. A buried strap is formed in each trench on the capacitor. The nitride pad layer is pulled back from the trench openings, exposing the pad oxide layer and any strap material that may have replaced the pad oxide layer around the trenches. The straps and trench sidewalls are doped to form a resistive connection. During a subsequent shallow trench isolation (STI) process, which involves an oxidation step, the exposed strap material on the surface of the silicon surface layer forms oxide unrestrained by pad nitride without stressing the silicon substrate.

摘要翻译： 一种在动态随机存取存储器（DRAM）单元中连接沟槽电容器的方法。 首先，在硅衬底中使用在衬垫氧化物层上包括衬垫氮化物层的掩模层形成沟槽。 沟槽电容器形成在沟槽中。 在电容器的每个沟槽中形成掩埋带。 氮化物衬垫层从沟槽开口被拉回，暴露衬垫氧化物层和可能已经替换衬垫氧化物层的任何带材料围绕沟槽。 带和沟槽侧壁被掺杂以形成电阻连接。 在随后的涉及氧化步骤的浅沟槽隔离（STI）工艺中，硅表面层表面上的暴露的带材料形成不受衬垫氮化物束缚的氧化物，而不会压迫硅衬底。

公开(公告)号：US06281539B1

公开(公告)日：2001-08-28

申请号：US09540854

申请日：2000-03-31

申请人： Jack A. Mandelman ,  Rama Divakaruni

发明人： Jack A. Mandelman ,  Rama Divakaruni

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/945

摘要： A 6F2 memory cell comprising a plurality of capacitors each located in a separate trench that is formed in a semiconductor substrate; a plurality of transfer transistors each having a vertical gate dielectric, a gate conductor, and a bitline diffusion, each transistor is located above and electrically connected to a respective trench capacitor; a plurality of dielectric-filled isolation trenches in a striped pattern about said transistors, said isolation trenches are spaced apart by a substantially uniform spacing; a respective wordline electrically contacted to each respective gate conductor, said wordline is in the same direction as the isolation stripes; and a bitline in contact with said bitline diffusion, wherein said bitline diffusions have a width that is defined by said spacing of said isolation trenches.

摘要翻译： 一种6F2存储单元，包括多个电容器，每个电容器均位于形成在半导体衬底中的单独的沟槽中; 每个具有垂直栅极电介质，栅极导体和位线扩散的多个转移晶体管，每个晶体管位于相应的沟槽电容器的上方并电连接到相应的沟槽电容器; 围绕所述晶体管的条纹图案的多个电介质填充的隔离沟槽，所述隔离沟槽间隔开大致均匀的间隔; 与每个相应的栅极导体电接触的相应字线，所述字线与隔离条相同; 以及与所述位线扩散接触的位线，其中所述位线扩散具有由所述隔离沟槽的所述间隔限定的宽度。

公开(公告)号：US06245651B1

公开(公告)日：2001-06-12

申请号：US09481916

申请日：2000-01-12

申请人： Rama Divakaruni ,  Larry Alan Nesbit ,  Carl John Radens

发明人： Rama Divakaruni ,  Larry Alan Nesbit ,  Carl John Radens

IPC分类号： H01L213205

CPC分类号： H01L27/10894 ,  H01L21/76802 ,  H01L27/10888

摘要： A method for simultaneously forming a line interconnect such as a bitline and a borderless contact to diffusion, e.g. bitline contact, is described. A semiconductor substrate having prepatterned gate stacks thereon is covered with a first dielectric to form a first level and then a second dielectric is deposited which forms a second level. Line interconnect openings are defined in the second level by lithography and etching. Etching is continued down to monocrystalline regions in an array region of the substrate to form borderless contact openings coincident to the line interconnects between the gate stacks. The openings are filled with one or more conductors to form contacts to diffusion, e.g. bitline contacts, which are coincident to the line interconnects, e.g. bitlines.

摘要翻译： 用于同时形成诸如位线和无边界接触之类的线互连的扩散的方法，例如。 描述了位线接触。 其上具有形成图案化栅极堆叠的半导体衬底被第一电介质覆盖以形成第一电平，然后沉积形成第二电平的第二电介质。 线路互连开口通过光刻和蚀刻在第二层限定。 在衬底的阵列区域中继续蚀刻到单晶区域以形成与栅叠层之间的线互连一致的无边界接触开口。 开口填充有一个或多个导体以形成扩散接触，例如。 位线接触，其与线互连一致，例如。 位线