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102 条记录 (耗时 0.034 秒)

    FLASH MEMORY STRUCTURE WITH ENHANCED CAPACITIVE COUPLING COEFFICIENT RATIO (CCCR) AND METHOD FOR FABRICATION THEREOF
    62.
    发明申请
    FLASH MEMORY STRUCTURE WITH ENHANCED CAPACITIVE COUPLING COEFFICIENT RATIO (CCCR) AND METHOD FOR FABRICATION THEREOF 失效
    具有增强电容耦合系数（CCCR）的闪存存储器结构及其制造方法

    公开(公告)号：US20120184076A1

    公开(公告)日：2012-07-19

    申请号：US13429556

    申请日：2012-03-26

    申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

    发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

    摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

    摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

    Laser annealing for 3-D chip integration
    63.
    发明授权
    Laser annealing for 3-D chip integration 有权
    激光退火3-D芯片集成

    公开(公告)号：US08138085B2

    公开(公告)日：2012-03-20

    申请号：US13093798

    申请日：2011-04-25

    申请人： Howard H. Chen ,  Louis C. Hsu ,  Lawrence S. Mok ,  J. Campbell Scott

    发明人： Howard H. Chen ,  Louis C. Hsu ,  Lawrence S. Mok ,  J. Campbell Scott

    IPC分类号： H01L21/44

    CPC分类号： H01L21/324 ,  H01L21/268 ,  H01L24/01 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00

    摘要： A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.

    摘要翻译： 公开了一种用于退火具有至少两个堆叠层的层叠半导体结构的激光退火方法。 激光束聚焦在堆叠层的下层。 然后扫描激光束以退火下层中的特征。 然后将激光束聚焦在堆叠层的上层上，并且激光束被扫描以退火上层中的特征。 激光器的波长小于1微米。 激光束的光束尺寸，焦深，能量投射和扫描速度是可编程的。 较低层中的特征偏离上层中的特征，使得这些特征不沿着与激光束的路径平行的平面重叠。 堆叠层中的每一个包括诸如晶体管的有源器件。 此外，第一层和第二层可以同时退火。

    SOI CMOS compatible multiplanar capacitor
    65.
    发明授权
    SOI CMOS compatible multiplanar capacitor 有权
    SOI CMOS兼容多平面电容器

    公开(公告)号：US07728371B2

    公开(公告)日：2010-06-01

    申请号：US11857770

    申请日：2007-09-19

    申请人： Kangguo Cheng ,  Louis C Hsu ,  Jack A. Mandelman ,  William Tonti

    发明人： Kangguo Cheng ,  Louis C Hsu ,  Jack A. Mandelman ,  William Tonti

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L28/60

    摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

    摘要翻译： 孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。 环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。 隔离的浅沟槽隔离部分和由导电材料的环限定的掩​​埋绝缘体层的部分被蚀刻以形成空腔。 在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。 形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个 第二电极。

    Interconnect structure and method for forming the same
    66.
    发明授权
    Interconnect structure and method for forming the same 有权
    互连结构及其形成方法

    公开(公告)号：US07727888B2

    公开(公告)日：2010-06-01

    申请号：US11216198

    申请日：2005-08-31

    申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

    发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

    IPC分类号： H01L29/41 ,  H01L21/44

    CPC分类号： H01L21/76814 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  Y10S438/964

    摘要： An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches will have a roughness of less than approximately 20 nm, and preferably less than approximately 10 nm. In addition to the via, gouge and trench(es), the interconnect structure of the present invention includes at least two levels of metal wiring. Further, in a typical embodiment, the interconnect structure utilizes any dielectrics having a dielectric constant no greater than approximately 5.0.

    摘要翻译： 描述了互连结构及其形成方法。 具体地说，在本发明中，在形成任何沟槽之前，在互连结构中形成的通孔内形成一个沟槽。 这防止了上述的沟槽损坏发生。 也就是说，沟槽的底表面将具有小于约20nm，优选小于约10nm的粗糙度。 除了通孔，沟槽和沟槽之外，本发明的互连结构还包括至少两层金属布线。 此外，在典型的实施例中，互连结构利用介电常数不大于约5.0的任何电介质。

    Microelectronic circuit structure with layered low dielectric constant regions and method of forming same
    68.
    发明授权
    Microelectronic circuit structure with layered low dielectric constant regions and method of forming same 失效
    具有层状低介电常数区域的微电子电路结构及其形成方法

    公开(公告)号：US07485567B2

    公开(公告)日：2009-02-03

    申请号：US11670524

    申请日：2007-02-02

    申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

    发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for manufacturing a microelectronic circuit includes the steps of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material; forming a plurality of alternating layers of layer dielectric material and sacrificial material over the first wiring level; and forming a plurality of interconnect openings and a plurality of gap openings in the alternating layers of layer dielectric material and sacrificial material. The interconnect openings are formed over the first wiring level conductors. The method further includes forming (i) metallic conductors comprising second wiring level conductors, and (ii) interconnects, at the interconnect openings; and removing the layers of the sacrificial material through the gap openings.

    摘要翻译： 一种制造微电子电路的方法包括以下步骤：提供包括由第一布线层介电材料隔开的第一布线层导体的第一布线层; 在所述第一布线层上形成层状介电材料和牺牲材料的多个交替层; 以及在层介电材料和牺牲材料的交替层中形成多个互连开口和多个间隙开口。 互连开口形成在第一布线层导体上。 该方法还包括形成（i）包括第二布线层导体的金属导体，和（ii）互连开口处的互连; 并且通过间隙开口去除牺牲材料的层。

    Fuse/anti-fuse structure and methods of making and programming same
    70.
    发明申请
    Fuse/anti-fuse structure and methods of making and programming same 有权
    保险丝/反熔丝结构及制作和编程方法相同

    公开(公告)号：US20080224261A1

    公开(公告)日：2008-09-18

    申请号：US12127080

    申请日：2008-05-27

    申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

    发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

    IPC分类号： H01L23/525 ,  H01L21/44

    CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor stricture Methods of making and programming the fuse/anti-fuse structures are also provided.

    摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中空腔限定结构的至少一部分由内部导体结构，绝缘层和外部导体狭窄中的至少一个形成。还提供了制造和编程熔丝/反熔丝结构的方法。