公开(公告)号：US07586350B2

公开(公告)日：2009-09-08

申请号：US11479689

申请日：2006-06-30

申请人： Jin-Il Chung ,  Chang-Ho Do

发明人： Jin-Il Chung ,  Chang-Ho Do

IPC分类号： H03K3/02

CPC分类号： H03K3/0375

摘要： Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an internal reset signal generating unit for generating an internal reset signal in response to a pad signal inputted from an arbitrary external pin during a test mode; an internal logic initializing signal generating unit for generating an internal logic initializing signal based on the power-up signal and the internal reset signal; and an internal logic unit initialized in response to the internal logic initializing signal.

摘要翻译： 提供一种半导体存储器件和驱动方法，用于在源极电压的稳定状态下初始化半导体存储器件内部的内部逻辑电路，而不需要额外的复位引脚。 半导体存储器件包括用于产生上电信号的上电信号产生单元; 内部复位信号产生单元，用于响应于在测试模式期间从任意外部引脚输入的焊盘信号产生内部复位信号; 内部逻辑初始化信号生成单元，用于基于所述上电信号和所述内部复位信号生成内部逻辑初始化信号; 以及响应于内部逻辑初始化信号而初始化的内部逻辑单元。

公开(公告)号：US20090067261A1

公开(公告)日：2009-03-12

申请号：US12288879

申请日：2008-10-24

申请人： Jae-Il Kim ,  Chang-Ho Do

发明人： Jae-Il Kim ,  Chang-Ho Do

IPC分类号： G11C7/00 ,  G11C8/16 ,  G11C8/00

CPC分类号： G11C7/1075 ,  G11C7/1027 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C8/16 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

摘要： A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

摘要翻译： 具有执行与外部设备的串行输入/输出（I / O）通信的多个端口的多端口存储器件以及通过多个全局I / O与端口执行并行I / O通信的多个存储体 线条。 多端口存储装置包括：写时钟生成单元，用于仅在应用写数据时选择性地切换写时钟; 写入控制单元，用于响应写入时钟和写入命令产生写入标志信号组和写入驱动器使能信号; 数据锁存单元，用于通过在写入标志信号组的控制下存储脉冲串写入数据来输出中间写入数据; 以及写入驱动器，用于接收中间写入数据，以响应于写入驱动器使能信号和数据掩码信号组而将最终写入数据写入相应存储体的存储器单元。

公开(公告)号：US07499356B2

公开(公告)日：2009-03-03

申请号：US11647685

申请日：2006-12-28

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/48 ,  G11C29/1201 ,  G11C29/26 ,  G11C2029/1802

摘要： A semiconductor device includes a plurality of first pads; a plurality of ports for performing a serial data communication with external devices through the first pads; a plurality of banks for performing a parallel data communication with the plurality of ports; a plurality of global data buses for supporting the parallel data communication between the plurality of ports and the plurality of banks; and a test mode controller for performing a core test with various data transfer modes by converting the serial data communication into the parallel data communication during a core test mode.

摘要翻译： 半导体器件包括多个第一焊盘; 用于通过第一焊盘执行与外部设备的串行数据通信的多个端口; 用于执行与所述多个端口的并行数据通信的多个存储体; 多个全球数据总线，用于支持多个端口和多个存储体之间的并行数据通信; 以及测试模式控制器，用于在核心测试模式期间通过将串行数据通信转换为并行数据通信来执行具有各种数据传输模式的核心测试。

公开(公告)号：US20080304354A1

公开(公告)日：2008-12-11

申请号：US12005964

申请日：2007-12-28

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： G11C8/18

CPC分类号： G11C8/18 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C29/36

摘要： A semiconductor memory device is capable of writing data in phase with external data to a memory cell regardless of which memory cell the data is written to. The semiconductor memory device includes a scrambler, a write selector and a read selector. The scrambler is configured to output a control signal activated when an address for accessing a memory cell of a complementary bit line is inputted. The write selector is configured to selectively transmit data of a write path in response to the control signal. The read selector is configured to selectively transmit data of a read path in response to the control signal

摘要翻译： 半导体存储器件能够将数据与外部数据同步地写入存储单元，而不管数据被写入哪个存储器单元。 半导体存储器件包括加扰器，写选择器和读选择器。 扰码器被配置为当输入用于访问互补位线的存储单元的地址时，输出激活的控制信号。 写选择器被配置为响应于控制信号选择性地发送写入路径的数据。 读选择器被配置为响应于控制信号选择性地发送读路径的数据

公开(公告)号：US20080239855A1

公开(公告)日：2008-10-02

申请号：US12156696

申请日：2008-06-03

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： The present invention relates to a semiconductor memory device to execute a refresh operation in such a manner that an entry and an exit of a self refresh mode is carried out. The present invention uses only external clock signals without a clock enable signal or an auto refresh command and therefore it is possible to implement a simple circuit for the self refresh. A semiconductor memory device includes a self refresh enable signal generator for outputting an activated self refresh enable signal when positive and negative external clock signals are in phase and a de-activated self refresh enable signal when the positive and negative external clock signals are out of phase and a self refresh block for performing a self refresh operation in response to the activated self refresh enable signal.

摘要翻译： 本发明涉及以执行自刷新模式的进入和退出的方式执行刷新操作的半导体存储器件。 本发明仅使用没有时钟使能信号或自动刷新命令的外部时钟信号，因此可以实现用于自刷新的简单电路。 一种半导体存储器件包括一个自刷新使能信号发生器，用于当正和负外部时钟信号同相时输出一个激活的自刷新使能信号，当正负外部时钟信号异相时，一个去激活的自刷新使能信号 以及自刷新块，用于响应于激活的自刷新使能信号执行自刷新操作。

公开(公告)号：US07414898B2

公开(公告)日：2008-08-19

申请号：US11139608

申请日：2005-05-31

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： G11C7/00

CPC分类号： G11C5/147

摘要： Provided is a semiconductor memory device including an internal power supply with low current consumption, which includes: an active interval security block for generating active interval security signals with operation intervals by a row active signal and a column active signal; an active driving signal generating block for generating an active driving signal, responsive to the active interval security signals; a standby driving block for holding the level of an internal voltage; and an active driving block, which is additionally driven based on the active driving signal to hold the internal voltage.

摘要翻译： 提供一种包括具有低电流消耗的内部电源的半导体存储器件，其包括：用于通过行有源信号和列活动信号产生具有操作间隔的有源间隔安全信号的有源间隔安全块; 用于响应于所述有效间隔安全信号产生有效驱动信号的有效驱动信号产生块; 备用驱动块，用于保持内部电压的电平; 以及有源驱动块，其基于有源驱动信号另外驱动以保持内部电压。

公开(公告)号：US07395475B2

公开(公告)日：2008-07-01

申请号：US10876210

申请日：2004-06-23

申请人： Chang-Ho Do

发明人： Chang-Ho Do

IPC分类号： G01R31/28

CPC分类号： G11C17/18 ,  G11C29/02 ,  G11C29/027 ,  G11C29/785

摘要： A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode is enabled; and a fuse set for providing a constant signal by using the output from the test mode enable confirmation section in case of the test mode, regardless of elimination or non-elimination of a fuse.

摘要翻译： 熔断器设置电路执行与保险丝切断之前相同的测试，即使在保险丝被切断的情况下也是如此。 为此，根据本发明的熔丝布置电路包括：测试模式使能确认部分，用于通知测试模式是否启用; 以及用于在测试模式的情况下使用来自测试模式使能确认部分的输出来提供恒定信号的熔丝组，而不管消除或不消除熔丝。

公开(公告)号：US20080074936A1

公开(公告)日：2008-03-27

申请号：US11903170

申请日：2007-09-20

申请人： Jae-Il Kim ,  Chang-Ho Do ,  Jin-Il Chung ,  Jae-Hyuk Im

发明人： Jae-Il Kim ,  Chang-Ho Do ,  Jin-Il Chung ,  Jae-Hyuk Im

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1075 ,  G11C7/1039 ,  G11C7/18 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C2207/108

摘要： A multi-port memory device includes a plurality of ports, a plurality of bank control units, a plurality of banks, a read clock generation unit, and a data transmission unit. Each of the banks is connected to a corresponding one of the bank control units. The read clock generation unit generates a read clock toggling for four clocks in response to a read command. The data transmission unit transmits a read data from the banks to a corresponding one of the ports in response to the read clock. Every bank control unit is connected to all of the ports.

摘要翻译： 多端口存储器件包括多个端口，多个存储体控制单元，多个存储体，读时钟生成单元和数据传输单元。 每个银行都连接到相应的一个银行控制单元。 读取时钟生成单元响应于读取命令产生四个时钟的读取时钟。 数据传输单元响应于读时钟将读取的数据从存储体发送到对应的一个端口。 每个银行控制单元连接到所有端口。

公开(公告)号：US20070126479A1

公开(公告)日：2007-06-07

申请号：US11478092

申请日：2006-06-30

申请人： Hwang Hur ,  Chang-Ho Do

发明人： Hwang Hur ,  Chang-Ho Do

IPC分类号： H03K19/00

CPC分类号： G11C29/34 ,  G11C7/1006 ,  G11C7/22 ,  G11C8/16 ,  G11C29/02 ,  G11C29/022 ,  G11C29/1201 ,  G11C2207/108

摘要： A signal aligning circuit includes a plurality of pads receiving input signals in parallel 1 bit by 1 bit; a first transferring unit for transferring the input signals as first signals in synchronization with a first clock signal of an internal clock, and transferring the input signals as second signals in synchronization with a second clock signal of the internal clock; a second transferring unit for transferring the first signals in synchronization with the second clock signal of the internal clock; and an aligning unit for aligning the first and second signals transferred from the first and second transferring units and outputting the aligned signal as output signals.

摘要翻译： 信号对准电路包括多个焊盘，1比特1比特并行地接收输入信号; 第一传送单元，用于将输入信号作为与内部时钟的第一时钟信号同步的第一信号传送，并且将输入信号作为与内部时钟的第二时钟信号同步的第二信号传送; 第二传送单元，用于与所述内部时钟的第二时钟信号同步地传送所述第一信号; 以及对准单元，用于对准从第一和第二传送单元传送的第一和第二信号，并输出对准的信号作为输出信号。

公开(公告)号：US07212461B2

公开(公告)日：2007-05-01

申请号：US11193145

申请日：2005-07-27

申请人： Jee-Yul Kim ,  Chang-Ho Do

发明人： Jee-Yul Kim ,  Chang-Ho Do

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C2211/4065

摘要： A memory device conducts a stable data access operation by removing glitch component in an internal clock outputted after a completion of self-refresh. This memory device includes a memory core region, a clock enable sensor for sensing an enable of a clock enable signal corresponding to a termination of a self-refresh operation to provide a sensing signal, a clock buffer for buffering a clock signal from the outside as an internal clock signal in response to the sensing signal and providing the internal clock signal to the memory core region, and a self-refresh control circuit for preventing a glitch component in the internal clock signal firstly outputted by the clock buffer in response to the sensing signal from transferring to the memory core region.

摘要翻译： 存储器件通过在完成自刷新之后输出的内部时钟中去除毛刺分量来进行稳定的数据存取操作。 该存储器件包括存储器核心区域，时钟使能传感器，用于检测对应于自刷新操作终止以提供感测信号的时钟使能信号的使能，用于从外部缓冲时钟信号的时钟缓冲器 响应于感测信号的内部时钟信号并将内部时钟信号提供给存储器核心区域;以及自刷新控制电路，用于防止由时钟缓冲器首先响应于感测而首先输出的内部时钟信号中的毛刺分量 从传输到存储器核心区域的信号。