公开(公告)号：US20230314180A1

公开(公告)日：2023-10-05

申请号：US18048627

申请日：2022-10-21

Applicant: Microchip Technology Incorporated

Inventor： Ganesh Shaga

IPC: G01D5/20

CPC classification number: G01D5/202

Abstract: Various examples include a target for an inductive angular-position sensor. The target may rotate about a center axis and may include a number of fins respectively including a respective outer-circumferential edge to overlap a respective first arc at least partially defining a first circle centered at the center axis. A respective first central angle of the respective first arc substantially equal to 360° divided by twice a count of the fins. The number of fins may respectively include a respective inner-circumferential edge, positioned closer to the center axis than the respective outer-circumferential edge is to the center axis. The respective inner-circumferential edge may overlap a respective second arc at least partially defining a second circle centered at the center axis. A respective second central angle of the respective second arc substantially equal to 360° divided by the count of the fins. Related devices, systems and methods are also disclosed.

公开(公告)号：US20230308098A1

公开(公告)日：2023-09-28

申请号：US18125789

申请日：2023-03-24

Applicant: Microchip Technology Incorporated

Inventor： Paul Schimel

IPC: H03K17/687 ,  H03K17/06 ,  H03K17/12

CPC classification number: H03K17/687 ,  H03K17/063 ,  H03K17/122

Abstract: An apparatus includes an apparatus input to receive a voltage input, an apparatus output to drive an output metal oxide semiconductor field effect transistor (MOSFET) at least partially based upon the voltage input, a current source circuit to provide a current source to the apparatus output when the voltage input rises above a first threshold and before the voltage input rises above a second threshold, a voltage clamp circuit to provide a clamped output voltage to the apparatus output when the voltage input rises above the second threshold, and a current sink circuit to provide a current sink to the apparatus output when the voltage input falls below the second threshold and before the voltage input reaches the first threshold.

公开(公告)号：US20230308084A1

公开(公告)日：2023-09-28

申请号：US18112812

申请日：2023-02-22

Applicant: Microchip Technology Incorporated

Inventor： Yong Yuenyongsgool ,  Stephen Bowing ,  Pedro Ovalle

IPC: H03K3/017 ,  G06F1/06 ,  H03K21/02

CPC classification number: H03K3/017 ,  G06F1/06 ,  H03K21/02

Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

公开(公告)号：US11764772B2

公开(公告)日：2023-09-19

申请号：US17304195

申请日：2021-06-16

Applicant: Microchip Technology Incorporated

Inventor： Albert J. Charpentier ,  Alan K. Smith ,  Nitesh Satheesh ,  Robin Weber

IPC: H03K17/04 ,  H03K3/012 ,  H03K5/24 ,  H03K17/042 ,  H03K17/16 ,  H03K21/08

CPC classification number: H03K17/0406 ,  H03K3/012 ,  H03K5/24 ,  H03K17/04206 ,  H03K17/168 ,  H03K21/08

Abstract: A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

公开(公告)号：US20230273977A1

公开(公告)日：2023-08-31

申请号：US18114261

申请日：2023-02-26

Applicant: Microchip Technology Incorporated

Inventor： Eileen Marando ,  Richard Wahler ,  Arun Krishnan ,  Randy Goldberg

IPC: G06F21/10

CPC classification number: G06F21/10 ,  G06F2221/2129

Abstract: A device with one-time-programmable (OTP) memory, boot code, volatile memory, and non-volatile memory. Boot code may use information in OTP to authenticate code of an implicit owner of the electronic device; receive a first create owner container request; create a first owner container comprising a first signed data image; store the first owner container; and use the first signed data image to authenticate first executable code associated with the first owner. Boot code may transfer ownership from the first owner to a second owner, including authenticating a signed transfer of ownership command using a key stored in the first owner container and creating a second owner container comprising a second signed data image associated with the second owner; storing the second owner container; revoking the first owner container; and using the second signed data image to authenticate second executable code associated with the second owner of the electronic device.

公开(公告)号：US20230268269A1

公开(公告)日：2023-08-24

申请号：US18140198

申请日：2023-04-27

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L23/532 ,  H01F27/32 ,  H01F27/28

CPC classification number: H01L23/5227 ,  H01L23/53238 ,  H01L23/53223 ,  H01F27/32 ,  H01L28/10 ,  H01F27/2823 ,  H01L23/5329

Abstract: A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.

公开(公告)号：US11729993B2

公开(公告)日：2023-08-15

申请号：US17409883

申请日：2021-08-24

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L21/00 ,  H10B53/30 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L28/55 ,  H01L28/65 ,  H01L28/92

Abstract: Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).

公开(公告)号：US20230223933A1

公开(公告)日：2023-07-13

申请号：US18153002

申请日：2023-01-11

Applicant: Microchip Technology Incorporated

Inventor： Perry Schugart

IPC: H03K3/012 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78

CPC classification number: H03K3/012 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7802

Abstract: An apparatus is disclosed that includes a common drain, a common source, and a common gate, respectively, of the power semiconductor device, and paralleled transistor cells of the power semiconductor device. In various examples, a configuration of a gate structure of a first respective transistor cell coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell coupled with the common gate. Alternatively or additionally, in various examples, a configuration of a structure coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a structure coupled between the second portion of the paralleled transistor cells and the common gate.

公开(公告)号：US20230207614A1

公开(公告)日：2023-06-29

申请号：US17744881

申请日：2022-05-16

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng

IPC: H01L49/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L28/87 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226

Abstract: A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and an insulator flange extending laterally outwardly from the insulator cup sidewall and extending laterally over an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the insulator flange.

公开(公告)号：US11689105B2

公开(公告)日：2023-06-27

申请号：US17381827

申请日：2021-07-21

Applicant: Microchip Technology Incorporated

Inventor： Simon Krugly

IPC: H02M3/158 ,  H02M1/00

CPC classification number: H02M3/1582 ,  H02M1/0025

Abstract: A multi-mode converter using iterative average current mode pulse width modulation (PWM) control is provided. The converter may include a current sense amplifier configured to output a current sense signal over a present switching cycle based on an inductor current through an inductor, a voltage error amplifier configured to output an error voltage based on a difference between a reference voltage and an output voltage, and a PWM controller. The PWM controller may include an error voltage modifier circuit configured to selectively output the error voltage or a modified error voltage based on a mode signal, and an iterative average current control circuit configured to generate a PWM signal based on the output from the error voltage modifier circuit, the current sense signal over the present switching cycle and a current sense signal over a previous switching cycle that precedes the present switching cycle.