公开(公告)号：US4855622A

公开(公告)日：1989-08-08

申请号：US134494

申请日：1987-12-18

申请人： Derrell Q. Johnson

发明人： Derrell Q. Johnson

IPC分类号： H03K19/088 ,  H03K17/16 ,  H03K17/615 ,  H03K17/66 ,  H03K19/003

CPC分类号： H03K19/00353 ,  H03K17/16 ,  H03K17/666

摘要： A TTL compatible buffer circuit responsive to an input signal and having a controlled ramp output is disclosed and includes a low and a high output voltage driver, each driver being comprised of a Darlington pair of transistors, and each driver being separately controlled by its own control circuit. Each control circuit includes at least a capacitor and resistor which are arranged to control the voltage at the base of the upper transistor of the Darlington pair output voltage driver. In this manner, the voltage at the high voltage driver increases in a substantially linear manner when the input signal goes from low to high, and the voltage at the low voltage driver decreases in a substantially linear manner when the input signal goes from high to low. The turn on time of the drivers is thus relatively long. Each control circuit further includes a transistor which permits the respective output voltage driver to turn off quickly. With a quick turn off and a long turn on, a break before make condition is established and voltage supply line bounce due to a feedthrough circuit is eliminated. Voltage supply line bounce due to current flow between the load capacitance at the buffer circuit output and a low voltage source through the low voltage driver upon the turning on of the low voltage driver is also substantially reduced.

公开(公告)号：US4794281A

公开(公告)日：1988-12-27

申请号：US822083

申请日：1986-01-24

申请人： Keith K. Onodera ,  Alex B. Djenguerian

发明人： Keith K. Onodera ,  Alex B. Djenguerian

IPC分类号： H03K19/00 ,  H03K19/013 ,  H03K19/088 ,  H03K3/33 ,  H03K5/13 ,  H03K17/16

CPC分类号： H03K19/001 ,  H03K19/0136

摘要： A totem-pole transistor circuit in the output stage of a logic device includes, in the base circuit of the current sink transistor, a discharge transistor responsive to each transition of a circuit input signal for discharging the parasitic base capacitance of the sink transistor, and a circuit for delaying the delivery of the input signal to the discharge transistor. The delay results in postponing the transition of the discharge transistor from one operational state to another. This causes the transitions of the discharge transistor to lag the transitions of the totem-pole pair which occur simultaneously with input signal changes. Thus, the discharge transistor is held on for a period of time sufficient to discharge the parasitic capacitance when the current-sink transistor turns off. This speeds up the turn-off of the sink transistor. After the period elapses, the discharge transistor turns off. Then, when base current is supplied to the current-sink transistor to turn it on, the discharge transistor is held off for an amount of time during which all of the base current is provided to the current-sink transistor, causing it to be quickly switched on. Then the discharge transistor is turned on, permitting it to discharge the parasitic capacitance of the current-sink transistor at the next input signal transition.

摘要翻译： 在逻辑器件的输出级中的图腾柱晶体管电路包括在电流吸收晶体管的基极电路中，对放电晶体管的寄生基极电容进行放电的电路输入信号的每个转变进行响应的放电晶体管，以及 用于延迟将输入信号传送到放电晶体管的电路。 延迟导致放电晶体管从一个操作状态转变到另一个操作状态。 这导致放电晶体管的转变滞后于与输入信号变化同时发生的图腾柱对的转变。 因此，放电晶体管保持导通一段时间，足以在导通晶体管截止时对寄生电容进行放电。 这将加速接收晶体管的关断。 经过一段时间后，放电晶体管截止。 然后，当将基极电流提供给电流沉降晶体管以使其导通时，放电晶体管被截止一段时间，在该时间期间，所有基极电流被提供给电流沉降晶体管，使得其快速 切换到。 然后放电晶体管导通，允许放电晶体管在下一个输入信号转变时放电电流吸收晶体管的寄生电容。

公开(公告)号：US4774620A

公开(公告)日：1988-09-27

申请号：US98768

申请日：1987-09-17

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Masao Kumagai ,  Akinori Tahara

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Masao Kumagai ,  Akinori Tahara

IPC分类号： H03K19/088 ,  H03K17/082 ,  H03K17/60 ,  H03K19/003 ,  H02H3/20

CPC分类号： H03K19/00307 ,  H03K17/0826

摘要： A logic circuit which reduces occurrence of breakdown of the pull-down transistor and pull-up transistor in the output stage when a high voltage is applied to the power supply line and ensures high voltage resistance. The logic circuit controls a pull-up transistor provided between a first power supply and an output terminal which turns ON and OFF in accordance with a collector voltage of a phase splitter transistor and controls the pull-down transistor provided between the second power supply and output terminal with an emitter voltage. Breakdown of the pull-down and pull-up transistors can be reduced and a high voltage resistance ensured by providing a protection circuit which discharges the base of the pull-down transistor and turns OFF the pull-down transistor by detecting when a voltage difference between the first power supply and the second power supply exceeds a specified value.

摘要翻译： 一种逻辑电路，当向电源线施加高电压并且确保高电压电阻时，减小输出级中的下拉晶体管和上拉晶体管的击穿的发生。 所述逻辑电路控制设置在第一电源和输出端之间的上拉晶体管，所述上拉晶体管根据分相晶体管的集电极电压而导通和截止，并控制所述第二电源和输出端之间提供的下拉晶体管 端子具有发射极电压。 可以减小下拉和上拉晶体管的故障，并通过提供一个保护电路来确保高电压电阻，该保护电路对下拉晶体管的基极进行放电，并通过检测下拉晶体管的电压差 第一电源和第二电源超过规定值。

公开(公告)号：US4749885A

公开(公告)日：1988-06-07

申请号：US15382

申请日：1987-02-17

申请人： Laszlo V. Gal

发明人： Laszlo V. Gal

IPC分类号： H03K19/082 ,  H03K19/088 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K19/082

摘要： A two input nonsaturating bipolar logic gate consists of just two bipolar transistors plus a pair of resistors plus two voltage buses. One resistor has a resistance R.sub.C and it is connected from one of the voltage buses to the collector of both transistors. The second resistor has a resistance R.sub.E and it is connected from the other voltage bus to the emitter of both transistors. Those resistances R.sub.C and R.sub.E are selected such that R.sub.C /R.sub.E >1 and 0.1

摘要翻译： 一个双输入非饱和双极逻辑门由两个双极晶体管和一对电阻加上两个电压总线组成。 一个电阻器具有电阻RC，并且从一个电压总线连接到两个晶体管的集电极。 第二电阻器具有电阻RE，并且从另一个电压总线连接到两个晶体管的发射极。 选择这些电阻RC和RE使得RC / RE> 1和0.1 <（VCC-VBE）RC / RE <0.8 VBE，其中VBE是每个晶体管导通的基极到发射极电压，VCC是两者之间的电压 电压母线

公开(公告)号：US4745308A

公开(公告)日：1988-05-17

申请号：US467681

申请日：1983-02-18

申请人： Eric D. Neely

发明人： Eric D. Neely

IPC分类号： H03K19/003 ,  H03K19/082 ,  H03K17/16 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/00353 ,  H03K19/0823

摘要： A three state gate having an output capable of assuming an active high, an active low, or a high impedance state is disclosed that eliminates a glitch in the output during the transition from the high impedance state to an active high. An output means includes a first transistor for supplying current to the output and a second transistor for draining current from the output. A phase splitting means determines the conductivity of the first and second transistors. A logic means is responsive to both an input signal and an output enable signal and is coupled to the phase splitting means. The logic means includes a level setting means that insures that the second transistor is not conductive during the transition of the output from the active high to the high impedance state.

摘要翻译： 公开了具有能够呈现有效高电平，有效低电平或高阻抗状态的输出的三态门，其消除了在从高阻抗状态向高电平跃迁期间的输出中的毛刺。 输出装置包括用于向输出端提供电流的第一晶体管和用于从输出引出电流的第二晶体管。 相位分离装置确定第一和第二晶体管的电导率。 逻辑装置响应输入信号和输出使能信号两者并耦合到相位分离装置。 逻辑装置包括电平设置装置，其确保在输出从有效高电平转换到高阻抗状态期间第二晶体管不导通。

公开(公告)号：US4740719A

公开(公告)日：1988-04-26

申请号：US928001

申请日：1986-11-07

申请人： Youichirou Taki

发明人： Youichirou Taki

IPC分类号： H03K19/088 ,  H03K19/013 ,  H03K19/20 ,  H03K3/01 ,  H03K3/33 ,  H03K17/16

CPC分类号： H03K19/0136

摘要： A semiconductor integrated circuit device including: a first transistor whose base receives an input signal, and whose collector is connected to a high power supply voltage; a second transistor whose base is conducted to the emitter of said first transistor and whose emitter is connected to a low power supply voltage; a third transistor whose base is connected to the collector of said first transistor, whose collector is connected to said high power supply voltage, and whose emitter is connected to the collector of said second transistor directly or via a load element; and a fourth transistor whose base is connected to the emitter of said third transistor, whose emitter is connected to said low power supply voltage, and from whose collector an output signal of said semiconductor integrated circuit device is taken out.

摘要翻译： 一种半导体集成电路器件，包括：第一晶体管，其基极接收输入信号，其集电极连接到高电源电压; 第二晶体管，其基极被传导到所述第一晶体管的发射极并且其发射极连接到低电源电压; 第三晶体管，其基极连接到所述第一晶体管的集电极，其集电极连接到所述高电源电压，并且其发射极直接或经由负载元件连接到所述第二晶体管的集电极; 以及第四晶体管，其基极连接到所述第三晶体管的发射极，其发射极连接到所述低电源电压，并且从其集电极连接所述半导体集成电路器件的输出信号。

公开(公告)号：US4713561A

公开(公告)日：1987-12-15

申请号：US15512

申请日：1987-02-10

申请人： Kazuyoshi Yamada

发明人： Kazuyoshi Yamada

IPC分类号： H03K17/04 ,  H03K19/013 ,  H03K19/0944 ,  H03K19/003 ,  H03K17/30 ,  H03K19/084 ,  H03K19/088

CPC分类号： H03K19/09448 ,  H03K19/013

摘要： A transistor circuit includes an input terminal, an output terminal, a first transistor having a collector connected to the output terminal, a second transistor having a collector-emitter passage connected between the collector of the first transistor and the input terminal, a PN junction element such as a diode or a base-emitter junction of another transistor, which is connected between the input terminal and the base of the first transistor, a first resistor connected between the emitter and base of the second transistor, and a second resistor connected between the base and collector of the second transistor.

摘要翻译： 晶体管电路包括输入端子，输出端子，具有连接到输出端子的集电极的第一晶体管，具有连接在第一晶体管的集电极和输入端子之间的集电极 - 发射极通道的第二晶体管，PN结元件 例如连接在第一晶体管的输入端子和基极之间的另一个晶体管的二极管或基极 - 发射极结，连接在第二晶体管的发射极和基极之间的第一电阻器，以及连接在第二晶体管的发射极和基极之间的第二电阻器 第二晶体管的基极和集电极。

公开(公告)号：US4709167A

公开(公告)日：1987-11-24

申请号：US408480

申请日：1982-08-16

申请人： Adrian P. Brokaw

发明人： Adrian P. Brokaw

IPC分类号： H03K19/0175 ,  H03K19/082 ,  H03K19/013 ,  H03K19/088

CPC分类号： H03K19/0826

摘要： A three-state output buffer delivering digital signals to a multi-line bus when in the data state, and presenting a high-impedance to the bus in the third state. The buffer output includes a two-transistor totem pole. Individual control transistor drivers are provided to switch the output transistors off when switching to the third state. The control transistors are actively driven both on and off. One of the output transistors includes an inverted-mode auxiliary collector which reduces base drive and saturation in that transistor, and which serves to hold off the other output transistor. Common control circuitry for all the buffer stages includes special means for reducing saturation effects to speed up control signals.

摘要翻译： 三态输出缓冲器在处于数据状态时将数字信号传送到多线总线，并且在第三状态下向总线呈现高阻抗。 缓冲器输出包括双晶体管图腾柱。 提供单独的控制晶体管驱动器以在切换到第三状态时将输出晶体管截止。 控制晶体管被主动地驱动和断开。 输出晶体管中的一个包括反相模式辅助集电极，其降低该晶体管的基极驱动和饱和，并且用于保持另一个输出晶体管。 所有缓冲级的通用控制电路包括减少饱和效应以加速控制信号的特殊装置。

公开(公告)号：US4704548A

公开(公告)日：1987-11-03

申请号：US697303

申请日：1985-01-31

申请人： Bobby D. Strong ,  Robert C. Martin ,  Kevin M. Ovens ,  James F. Salzman

发明人： Bobby D. Strong ,  Robert C. Martin ,  Kevin M. Ovens ,  James F. Salzman

IPC分类号： H03K19/0175 ,  H03K19/013 ,  H03K19/082 ,  H03K19/088 ,  H03K19/01 ,  H03K17/04 ,  H03K17/60

CPC分类号： H03K19/088 ,  H03K19/0136 ,  H03K19/0826

摘要： The specification discloses an input transistor (14) which is variable between high and low impedance states in response to input voltage transitions at terminal 10. An output transistor (16) is coupled to the input transistor (14) and is responsive to an input transition at terminal 10 for changing impedance states. Circuitry including a speed up transistor (44) is coupled between the input transistor (14) and output transistor (16) for applying added current to the output transistor (16) to speed the change of impedance state. The circuitry applies added current to output transistor (16) until the output voltage at terminal (18) falls below twice the base-emitter voltage of the output transistor (16).

摘要翻译： 本说明书公开了一种输入晶体管（14），其响应于端子10处的输入电压跃迁而在高阻抗状态和低阻抗状态之间是可变的。输出晶体管（16）耦合到输入晶体管（14）并响应于输入转换 在端子10处用于改变阻抗状态。 包括加速晶体管（44）的电路耦合在输入晶体管（14）和输出晶体管（16）之间，用于向输出晶体管（16）施加相加的电流以加速阻抗状态的改变。 电路对输出晶体管（16）施加相加的电流，直到端子（18）的输出电压下降到输出晶体管（16）的基极 - 发射极电压的两倍以下。

公开(公告)号：US4703202A

公开(公告)日：1987-10-27

申请号：US700413

申请日：1985-02-11

申请人： Hiromu Enomoto ,  Yasushi Yasuda ,  Akinori Tahara ,  Masao Kumagai

发明人： Hiromu Enomoto ,  Yasushi Yasuda ,  Akinori Tahara ,  Masao Kumagai

IPC分类号： G06F13/14 ,  G06F7/00 ,  H03K3/286 ,  H03K3/356 ,  H03K5/04 ,  H03K5/151 ,  H03K19/003 ,  H03K19/013 ,  H03K19/088

CPC分类号： H03K19/00307 ,  H03K19/00353 ,  H03K19/013 ,  H03K5/151

摘要： A gate circuit used for controlling an interface circuit in a microcomputer system, including a first-stage gate circuit, a second-stage gate circuit, and a control device connected between the first-stage gate circuit and the second-stage gate circuit. The first-stage gate circuit outputs an inverted strobe signal to the interface circuit, and the second-stage gate circuit outputs a non-inverted strobe signal to the interface circuit. Although there is a time lag in the changeover timing of these strobe signals, this time lag is reduced by connected the diode between the first-stage gate circuit and the second-stage gate circuit.

摘要翻译： 一种用于控制微机系统中的接口电路的门电路，包括连接在第一级门电路和第二级门电路之间的第一级门电路，二级门电路和控制装置。 第一级门电路向接口电路输出反相选通信号，第二级门电路向接口电路输出非反相选通信号。 尽管这些选通信号的转换定时存在时间滞后，但是通过连接第一级门电路和第二级门电路之间的二极管来减小该时滞。