公开(公告)号：US20210405968A1

公开(公告)日：2021-12-30

申请号：US17029836

申请日：2020-09-23

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Bin HE ,  Shubh SHAH ,  Michael MANTOR

IPC分类号： G06F7/57 ,  G06F17/16 ,  G06N3/08

摘要： A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.

公开(公告)号：US20210318856A1

公开(公告)日：2021-10-14

申请号：US17050359

申请日：2019-04-15

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Takayuki IKEDA ,  Roh YAMAMOTO ,  Shuichi KATSUI

IPC分类号： G06F7/60 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G06F7/57 ,  G06N3/08

摘要： A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.

公开(公告)号：US20210303307A1

公开(公告)日：2021-09-30

申请号：US16834833

申请日：2020-03-30

申请人： Arm Limited

发明人： Jens OLSON ,  John Wakefield BROTHERS, III ,  Jared Corey SMOLENS ,  Chi-wen CHENG ,  Daren CROXFORD ,  Sharjeel SAEED ,  Dominic Hugo SYMES

IPC分类号： G06F9/345 ,  G06F9/30 ,  G06F9/38 ,  G06F7/57 ,  G06F7/499

摘要： Herein described is a method of operating an accumulation process in a data processing apparatus. The accumulation process comprises a plurality of accumulations which output a respective plurality of accumulated values, each based on a stored value and a computed value generated by a data processing operation. The method comprises storing a first accumulated value, the first accumulated value being one of said plurality of accumulated values, into a first storage device comprising a plurality of single-bit storage elements; determining that a predetermined trigger has been satisfied with respect to the accumulation process; and in response to the determining, storing at least a portion of a second accumulated value, the second accumulated value being one of said plurality of accumulated values, into a second storage device.

公开(公告)号：US20210294574A1

公开(公告)日：2021-09-23

申请号：US17191848

申请日：2021-03-04

申请人： DENSO TEN Limited

发明人： Dongliang FAN ,  Hironori YOHATA ,  Shigeto UMEYAMA

IPC分类号： G06F7/57 ,  G06F5/01 ,  G06F15/80

摘要： An electronic control apparatus includes a first arithmetic processor and a second arithmetic processor that is communicably connected to the first arithmetic processor. The second arithmetic processor includes a controller configured to (i) shift to a rewriting wait state after outputting a request signal that requests a program rewriting to the first arithmetic processor, and (ii) release the rewriting wait state and shift to a program rewriting process after a predetermined wait time that allows the first arithmetic processor to shift to the program rewriting process elapses after outputting the request signal.

公开(公告)号：US20210271488A1

公开(公告)日：2021-09-02

申请号：US17255710

申请日：2019-05-21

申请人： VSORA

发明人： Khaled Maalej ,  Trung-Dung Nguyen ,  Julien Schmitt ,  Pierre-Emmanuel Bernard

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06F15/78 ,  G06F7/57

摘要： A computing device comprising: a plurality of ALUs; a set of registers; a memory; a memory interface between the registers and the memory; a control unit controlling the ALUs by generating: at least one cycle i including both implementing at least one first computing operation by way of an arithmetic logic unit and downloading a first dataset from the memory to at least one register; at least one cycle ii, following the at least one cycle i, including implementing a second computing operation by way of an arithmetic logic unit, for which second computing operation at least part of the first dataset forms at least one operand.

公开(公告)号：US11106462B2

公开(公告)日：2021-08-31

申请号：US16589118

申请日：2019-09-30

申请人： Texas Instruments Incorporated

发明人： Timothy David Anderson ,  Mujibur Rahman

IPC分类号： G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/48 ,  G06F7/57

摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

公开(公告)号：US11093578B2

公开(公告)日：2021-08-17

申请号：US16564788

申请日：2019-09-09

申请人： FUJITSU LIMITED

发明人： Noboru Yoneoka

IPC分类号： G06F17/11 ,  G06F7/57 ,  G06F7/58

摘要： An optimization device includes M-stage arithmetic processing circuits connected in a ring shape, wherein each circuit determines whether to permit updating for each of first bits, a number of the first bits being obtained by dividing a number of second bits corresponding to all spins of an Ising model by M; selects one update candidate bit from among update permission bits; and updates a value of any one of the second bits based on identification information supplied from a last stage circuit to a top stage circuit, wherein each circuit other than the top stage circuit selects identification information of the one update candidate bit at a first probability obtained by dividing a number of the update permission bits by a sum of the number of the update permission bits and a number supplied from a previous stage circuit, and supplies the selected identification information to a subsequent stage circuit.

公开(公告)号：US11086634B2

公开(公告)日：2021-08-10

申请号：US16698993

申请日：2019-11-28

申请人： Shanghai Cambricon Information Technology Co., Ltd.

发明人： Zai Wang ,  Xuda Zhou ,  Zidong Du ,  Tianshi Chen

IPC分类号： H03M13/00 ,  G06F9/38 ,  G06F9/30 ,  G06F17/16 ,  G06F3/01 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F11/07 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0875 ,  G06K9/00 ,  G06K9/62 ,  G06N3/04 ,  G06N3/063 ,  G06F7/57

摘要： The disclosure provides a data processing device and method. The data processing device may include: a task configuration information storage unit and a task queue configuration unit. The task configuration information storage unit is configured to store configuration information of tasks. The task queue configuration unit is configured to configure a task queue according to the configuration information stored in the task configuration information storage unit. According to the disclosure, a task queue may be configured according to the configuration information.

公开(公告)号：US20210216282A1

公开(公告)日：2021-07-15

申请号：US17004228

申请日：2020-08-27

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takao MARUKAME ,  Koichi MIZUSHIMA ,  Kumiko NOMURA ,  Yoshifumi NISHI

IPC分类号： G06F7/57 ,  G06F7/503 ,  G05F3/22 ,  G06F9/30

摘要： According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.

公开(公告)号：US20210200836A1

公开(公告)日：2021-07-01

申请号：US17137226

申请日：2020-12-29

申请人： QUALCOMM Incorporated

发明人： Yun DU ,  Gang ZHONG ,  Fei WEI ,  Yibin ZHANG ,  Jing HAN ,  Hongjiang SHANG ,  Elina KAMENETSKAYA ,  Minjie HUANG ,  Alexei Vladimirovich BOURD ,  Chun YU ,  Andrew Evan GRUBER ,  Eric DEMERS

IPC分类号： G06F17/16 ,  G06F7/57

摘要： The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.