公开(公告)号：US06529945B1

公开(公告)日：2003-03-04

申请号：US09361079

申请日：1999-07-26

申请人： George Michael Calhoun ,  David Charles Sips ,  Edward Stanley Suffern

发明人： George Michael Calhoun ,  David Charles Sips ,  Edward Stanley Suffern

IPC分类号： G06F15167

CPC分类号： H04L49/90

摘要： A data buffer management system and method between two different types of systems, The data buffer management system employs circular buffer chaining, wherein multiple state machines service buffer updates from multiple sources, dual buffer structures are maintained, mapping is provided between two different control block structures, and full duplex operation is supported. The data buffer management system manages use of a data buffer memory. A transmit operation is performed by transferring and storing data from one of the two different systems to the data buffer memory The data in the data buffer memory is converted and read by another of the two different systems. A receive operation is performed by transferring and storing data from the other of the two different systems to the data buffer memory.

摘要翻译： 两种不同类型系统之间的数据缓冲管理系统和方法，数据缓冲管理系统采用循环缓冲链接，其中多个状态机从多个源服务缓冲区更新，保持双缓冲结构，在两个不同的控制块结构之间提供映射 ，并支持全双工操作。 数据缓冲管理系统管理数据缓冲存储器的使用。 通过将数据从两个不同系统之一传送并存储到数据缓冲存储器来执行发送操作。数据缓冲存储器中的数据被两个不同系统中的另一个转换和读取。 通过将来自两个不同系统中的另一个的数据传送和存储到数据缓冲存储器来执行接收操作。

公开(公告)号：US06457047B1

公开(公告)日：2002-09-24

申请号：US09566675

申请日：2000-05-08

申请人： Ashok Chandra ,  Neil LaTarche ,  Jianchang Mao ,  Prabhakar Raghavan

发明人： Ashok Chandra ,  Neil LaTarche ,  Jianchang Mao ,  Prabhakar Raghavan

IPC分类号： G06F15167

CPC分类号： G06F17/30902

摘要： An application caching system and method are provided wherein one or more applications may be cached throughout a distributed computer network. The system may include a central cache directory server, one or more distributed master application servers and one or more distributed application cache servers. The system may permit a service, such as a search, to be provided to the user more quickly.

摘要翻译： 提供了应用缓存系统和方法，其中可以在整个分布式计算机网络中缓存一个或多个应用。 该系统可以包括中央缓存目录服务器，一个或多个分布式主应用服务器和一个或多个分布式应用缓存服务器。 系统可以允许更快地向用户提供诸如搜索的服务。

公开(公告)号：US06421711B1

公开(公告)日：2002-07-16

申请号：US09106299

申请日：1998-06-29

申请人： Steven M. Blumenau ,  Yoav Raz

发明人： Steven M. Blumenau ,  Yoav Raz

IPC分类号： G06F15167

CPC分类号： H04L61/35 ,  G06F3/0605 ,  G06F3/0617 ,  G06F3/0635 ,  G06F3/0662 ,  G06F3/067 ,  H04L29/12009 ,  H04L29/12783 ,  H04L67/28 ,  H04L67/2819 ,  H04L69/329

摘要： A storage controller has at least one physical data port for a data network including host processors. The storage controller is programmed to provide a plurality of virtual ports for access to storage, and a virtual switch for routing storage access requests from the physical port to the virtual ports. The virtual ports and the virtual switch are defined by software. The virtual ports appear to the hosts as physical ports in the data network. For example, in a Fiber-Channel network, the virtual ports have World Wide Names (WWNs) and are assigned temporary addresses (S_Ds), and the virtual switch provides a name server identifying the WWNs and S_IDs of the virtual ports. For convenient partitioning of storage among host processors, one or more virtual ports are assigned to each host, and a set of storage volumes are made accessible from each virtual port. A host can access storage at a virtual port only if the virtual port has been assigned to the host. Preferably, storage can be accessed through each virtual port by no more than one assigned host, although a shared volume may be accessible from more than one virtual port. The storage controller may provide a service for reporting to a host the virtual ports through which the host can access storage, and the storage volumes that are accessible to the host through each of the virtual ports.

摘要翻译： 存储控制器具有用于包括主处理器的数据网络的至少一个物理数据端口。 存储控制器被编程为提供用于访问存储的多个虚拟端口，以及用于将存储访问请求从物理端口路由到虚拟端口的虚拟交换机。 虚拟端口和虚拟交换机由软件定义。 虚拟端口作为数据网络中的物理端口显示给主机。 例如，在光纤通道网络中，虚拟端口具有万维网名称（WWN），并分配临时地址（S_Ds），虚拟交换机提供标识虚拟端口的WWN和S_ID的名称服务器。 为了方便主机处理器之间的存储划分，一个或多个虚拟端口被分配给每个主机，并且一组存储卷可从每个虚拟端口访问。 仅当虚拟端口已分配给主机时，主机才能访问虚拟端口上的存储。 优选地，可以通过不超过一个分配的主机的每个虚拟端口来访问存储，尽管可以从多于一个虚拟端口访问共享卷。 存储控制器可以提供用于向主机报告主机可以访问存储的虚拟端口的服务以及主机通过每个虚拟端口可访问的存储卷。

公开(公告)号：US06377979B1

公开(公告)日：2002-04-23

申请号：US09210646

申请日：1998-12-14

申请人： Toshiro Yamashita ,  Toshiaki Shimoda ,  Tetsuya Takahashi ,  Kazushige Harada

发明人： Toshiro Yamashita ,  Toshiaki Shimoda ,  Tetsuya Takahashi ,  Kazushige Harada

IPC分类号： G06F15167

CPC分类号： H04L29/06 ,  H04L67/1002

摘要： A multiple-processor system uses transfer blocks each having a size equal to or less than the capacity of a shared memory when transferring data from a master system to a slave system via the shared memory. Each transfer block includes a data to be transferred from the master system or a plurality of divisional data obtained by dividing the data to be transferred; information representing a writing-start address at which the data to be transferred or the plurality of divisional data starts to be written in storage for the slave system; and information representing the length of the data or the plurality of divisional data.

摘要翻译： 当通过共享存储器将数据从主系统传送到从系统时，多处理器系统使用各自具有等于或小于共享存储器容量的传输块。 每个传送块包括要从主系统传送的数据或通过划分要传送的数据获得的多个分割数据; 表示要传送的数据或多个分割数据的写入开始地址的信息开始被写入用于从系统的存储器中; 以及表示数据长度或多个分割数据的信息。

公开(公告)号：US06219072B1

公开(公告)日：2001-04-17

申请号：US09160860

申请日：1998-09-25

申请人： Keisuke Tanaka ,  Takahiro Ochi

发明人： Keisuke Tanaka ,  Takahiro Ochi

IPC分类号： G06F15167

CPC分类号： G09G5/363 ,  H04N5/44504

摘要： Disposed in a single integrated circuit chip are a central processing unit (CPU) for performing instruction execution, an on-screen display (OSD) circuit for displaying character information on a display screen, a read only memory (ROM) which is arbitrarily divided into a first ROM storage space for use by the CPU and a second ROM storage space for use by the OSD circuit, a random access memory (RAM) which is arbitrarily divided into a first RAM storage space for use by the CPU and a second RAM storage space for use by the OSD circuit, and a common bus which is composed of a data bus and an address bus. The CPU, the OSD circuit, the ROM, and the RAM are connected to the common bus in such a way as to allow the CPU and the OSD circuit to acquire an exclusive right to use the ROM and the RAM. When the common bus is not in use by the CPU, a message that said common bus is made available to the OSD circuit is communicated from the CPU to the OSD circuit via a bus liberation signal line, and the OSD circuit obtains a right to use the common bus.

摘要翻译： 在单个集成电路芯片中设置用于执行指令执行的中央处理单元（CPU），用于在显示屏幕上显示字符信息的屏幕显示（OSD）电路，任意分割为只读存储器 用于CPU使用的第一ROM存储空间和用于由OSD电路使用的第二ROM存储空间;随机存取存储器（RAM），其被任意划分为由CPU使用的第一RAM存储空间和第二RAM存储器 由OSD电路使用的空间，以及由数据总线和地址总线组成的公共总线。 CPU，OSD电路，ROM和RAM连接到公共总线，以允许CPU和OSD电路获得使用ROM和RAM的专有权。 当公共总线未被CPU使用时，通过总线释放信号线将通向总线的OSD电路可用的消息从CPU传送到OSD电路，并且OSD电路获得使用权 公车。

公开(公告)号：US06182121B2

公开(公告)日：2001-01-30

申请号：US09128922

申请日：1998-08-04

申请人： Scott Wlaschin

发明人： Scott Wlaschin

IPC分类号： G06F15167

CPC分类号： G06F17/30168 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99938

摘要： A distributed storage system provides a method and apparatus for storing, retrieving, and sharing data items across multiple physical storage devices that may not always be connected with one another. The present invention comprises one or more ‘partitions’ on distinct storage devices, with each partition comprising of a group of associated data files. Partitions can be of various types, and the partitions of the various clients may, at various times, be merged into a consolidation file or a file resident within another partition. The system resolves conflicts between two or more clients to determine which updates, if any, should be stored in a library partition. The flexible, self-referential table of the present invention may store any type of data, both structured and unstructured, and provides an interface to other application programs. The table of the present invention comprises a plurality of rows and columns. Each row has an object identification number (OID) and each column also has an OID. A row corresponds to a record and a column corresponds to a field such that the intersection of a row and a column comprises a cell that may contain data for a particular record related to a particular field, a cell may also point to another record. To enhance searching and to provide for synchronization between columns, columns are entered as rows in the table and the record corresponding to a column contains various information about the column. The table includes an index structure for extended queries.

摘要翻译： 分布式存储系统提供了一种用于在跨多个物理存储设备上存储，检索和共享数据项的方法和装置，其可能不总是彼此连接。 本发明包括在不同存储设备上的一个或多个“分区”，每个分区包括一组相关联的数据文件，分区可以是各种类型，并且各种客户端的分区可以在不同的时间被合并成 合并文件或驻留在另一个分区中的文件，系统解决两个或多个客户端之间的冲突，以确定哪些更新（如果有的话）应存储在库分区中。本发明的灵活的自引用表可以存储任何 数据类型，结构化和非结构化，并且提供与其他应用程序的接口。本发明的表包括多行和列，每行具有对象标识号（OID），并且每列还具有OID。 行对应于记录，并且列对应于字段，使得行和列的交集包括可以包含用于特定记录的数据的单元 对于特定字段，单元还可以指向另一记录。 为了增强搜索和提供列之间的同步，列作为表中的行输入，对应于列的记录包含有关列的各种信息。 该表包括用于扩展查询的索引结构。

公开(公告)号：US06816889B1

公开(公告)日：2004-11-09

申请号：US09897458

申请日：2001-07-03

申请人： Stanley Graham

发明人： Stanley Graham

IPC分类号： G06F15167

CPC分类号： H04L29/06 ,  H04L69/12

摘要： An InfiniBand™ computing node includes a dual port memory configured for storing data for a CPU and a host channel adapter in a manner that eliminates contention for access to the dual port memory. The dual port memory includes first and second memory ports, memory banks for storing data, and addressing logic configured for assigning first and second groups of the memory banks to the respective memory ports based on prescribed assignment information. The host channel adapter is configured for accessing the dual port memory via the first memory port, and the CPU is configured for accessing the dual port memory via the second memory port. The CPU also is configured for providing the prescribed assignment information to the addressing logic, enabling the host channel adapter to access the first group of memory banks via the first memory port as the CPU concurrently accesses the second group of memory banks via the second memory port. The CPU also dynamically reassigns the memory banks, enabling the host channel adapter to continue accessing the second group of memory banks via the first memory port, concurrent with the CPU accessing the first group of memory banks via the second memory port.

摘要翻译： InfiniBand TM计算节点包括双端口存储器，其被配置为以消除对双端口存储器的访问的争用的方式存储CPU和主机信道适配器的数据。 双端口存储器包括第一和第二存储器端口，用于存储数据的存储器组和用于基于规定的分配信息将存储体组的第一组和第二组分配给相应的存储器端口的寻址逻辑。 主机通道适配器被配置为经由第一存储器端口访问双端口存储器，并且CPU被配置为经由第二存储器端口访问双端口存储器。 CPU还被配置为向寻址逻辑提供规定的分配信息，使得主机通道适配器经由第一存储器端口访问第一组存储体，因为CPU经由第二存储器端口同时访问第二组存储器组 。 CPU还动态地重新分配存储体，使得主机通道适配器可以经由第一存储器端口继续访问第二组存储器组，与CPU同时通过第二存储器端口访问第一组存储器组。

公开(公告)号：US06795848B1

公开(公告)日：2004-09-21

申请号：US09708134

申请日：2000-11-08

申请人： John Border ,  Douglas Dillon ,  Matt Butehorn

发明人： John Border ,  Douglas Dillon ,  Matt Butehorn

IPC分类号： G06F15167

CPC分类号： G06F17/30902 ,  H04L29/06 ,  H04L67/02 ,  H04L67/142 ,  H04L67/28 ,  H04L67/2828 ,  H04L67/2852 ,  H04L67/42 ,  H04L69/16 ,  H04L69/163

摘要： A communication system for retrieving web content is disclosed. A downstream proxy server receives a URL request message from a web browser, in which the URL request message specifies a URL content that has an embedded object. An upstream proxy server receives the URL request message from the downstream proxy server. The upstream proxy server selectively forwards the URL request message to a web server and receives the URL content from the web server, wherein the upstream proxy server forwards the URL content to the downstream proxy server and parses the URL content to obtain the embedded object prior to receiving a corresponding embedded object request message initiated by the web browser.

摘要翻译： 公开了一种用于检索网页内容的通信系统。 下游代理服务器从Web浏览器接收URL请求消息，其中URL请求消息指定具有嵌入对象的URL内容。 上游代理服务器从下游代理服务器接收URL请求消息。 上游代理服务器选择性地将URL请求消息转发到web服务器并从Web服务器接收URL内容，其中上游代理服务器将URL内容转发到下游代理服务器，并解析URL内容以在 接收由web浏览器发起的对应的嵌入对象请求消息。

公开(公告)号：US06772199B1

公开(公告)日：2004-08-03

申请号：US09661661

申请日：2000-09-14

申请人： Thomas Walter Keller, Jr. ,  Karthikeyan P. Sankaralingam

发明人： Thomas Walter Keller, Jr. ,  Karthikeyan P. Sankaralingam

IPC分类号： G06F15167

CPC分类号： G06F17/30902 ,  G06F12/126 ,  H04L67/02

摘要： A method and system for enhanced cache efficiency is a cache associated with a server in a wide area network having multiple servers and clients. Objects retrieved from the network by a server are stored within a cache associated with the server and selected objects are designated as temporarily exempt from replacement based upon a preselected criterion, such as size or mandated quality of service for the client which requested the object. After the cache is full or nearly full, subsequently retrieved objects are stored by casting out one or more objects which are not exempt from replacement according to a specified replacement algorithm, such as Least Recently Utilized, or by casting out any object or objects, if all objects in the cache are designated as exempt from replacement.

摘要翻译： 用于增强高速缓存效率的方法和系统是与具有多个服务器和客户端的广域网中的服务器相关联的高速缓存。 由服务器从网络检索的对象被存储在与服务器相关联的高速缓存中，并且基于预先选择的标准（例如请求对象的客户端的规定或强制服务质量），将所选择的对象指定为暂时不被替换。 在缓存已满或接近完成之后，通过根据指定的替换算法（例如“最近最少使用”）或通过抛出任何对象或对象来抛出一个或多个不被替换的对象来存储后续检索对象，如果 缓存中的所有对象都被指定为免除替换。

公开(公告)号：US06753873B2

公开(公告)日：2004-06-22

申请号：US09774554

申请日：2001-01-31

申请人： Walter Vincent Dixon ,  Nick Andrew Van Stralen ,  Edward James Nieters

发明人： Walter Vincent Dixon ,  Nick Andrew Van Stralen ,  Edward James Nieters

IPC分类号： G06F15167

CPC分类号： A61B6/56 ,  A61B6/541 ,  G01N23/046 ,  G01N2223/419 ,  G01N2223/612 ,  H04N5/32

摘要： An imaging system shares control of host memory between a detector framing node and a host processor. The detector framing node is programmable to control generation and reception of image data. Image data is acquired and communicated to host memory independently from control by a host operating system. The detector framing node controls events according to an event instruction sequence and communicates received image data to the host memory through a computer communication bus. Image data is received by the detector framing node from a flat panel detector. Host memory has a first section managed by the host operating system and a second section not managed by the host operating system. Image data is communicated from the detector framing node into the second section of host memory. Event instruction sequences are communicated from the first section of host memory to the detector framing node to control the generation and reception of image data.

摘要翻译： 成像系统共享检测器成帧节点和主机处理器之间的主机存储器的控制。 检测器成帧节点是可编程的，用于控制图像数据的生成和接收。 获取图像数据并将其与主机操作系统的控制独立地传送到主机存储器。 检测器成帧节点根据事件指令序列控制事件，并通过计算机通信总线将接收的图像数据传送到主机存储器。 图像数据由检测器框架节点从平板检测器接收。 主机内存具有由主机操作系统管理的第一部分和不由主机操作系统管理的第二部分。 图像数据从检测器成帧节点传送到主机存储器的第二部分。 事件指令序列从主机存储器的第一部分传送到检测器成帧节点，以控制图像数据的生成和接收。