Abstract:
A rotary moulding machine for biscuit dough of the kind comprising a pair of co-operating rolls defining the bottom of a dough hopper, one roll having an embossed surface for feeding dough downwardly and into contact with the surface of the other or moulding roll which is formed with moulding recesses, and a scraper blade mounted to bear against the surface of the latter roll so as to press dough into the moulding recesses and remove excess dough from the remainder of the surface, includes the improvement that the scraper blade is carried by a pivoted mounting capable of infinitely variable adjustment along a path which guides the mounting in a direction having at least a substantial vertical component and a biasing arrangement is provided which exerts a turning moment on the mounting about the pivotal axis so as to press the scraper blade against the surface of the moulding roll. The machine may include a detector for measuring the average weight of resultant moulded dough pieces either directly or indirectly and a power-operated device responsive to the output of the detector for adjusting the position of the mounting in accordance with variations in the average weight. The power operated device may be a servomotor and the path of adjustment of the mounting may be defined by a slot co-operating with a pin defining the pivotal axis, relative movement between the two being controlled by a rotary cam.
Abstract:
An InfiniBand™ computing node includes a dual port memory configured for storing data for a CPU and a host channel adapter in a manner that eliminates contention for access to the dual port memory. The dual port memory includes first and second memory ports, memory banks for storing data, and addressing logic configured for assigning first and second groups of the memory banks to the respective memory ports based on prescribed assignment information. The host channel adapter is configured for accessing the dual port memory via the first memory port, and the CPU is configured for accessing the dual port memory via the second memory port. The CPU also is configured for providing the prescribed assignment information to the addressing logic, enabling the host channel adapter to access the first group of memory banks via the first memory port as the CPU concurrently accesses the second group of memory banks via the second memory port. The CPU also dynamically reassigns the memory banks, enabling the host channel adapter to continue accessing the second group of memory banks via the first memory port, concurrent with the CPU accessing the first group of memory banks via the second memory port.