公开(公告)号：US20030204705A1

公开(公告)日：2003-10-30

申请号：US10134649

申请日：2002-04-30

Inventor： William H. Oldfield ,  Alexander E. Nancekievill

IPC: G06F009/00

CPC classification number: G06F9/3844 ,  G06F9/30054 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3806

Abstract: The present invention provides a data processing apparatus and method for predicting branch instructions in a data processing apparatus. The data processing apparatus comprises a processor for executing instructions, a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor for execution, and branch prediction logic for predicting which instruction should be prefetched by the prefetch unit. The branch prediction logic is arranged to predict whether a prefetched instruction specifies a branch operation that will cause a change in instruction flow, and if so to indicate to the prefetch unit a target address within the memory from which a next instruction should be retrieved. The instructions include a first instruction and a second instruction that are executable independently by the processor, but which in combination specify a predetermined branch operation whose target address is uniquely derivable from a combination of attributes of the first and second instruction. The data processing apparatus further comprises target address logic for deriving from the combination of attributes the target address for the predetermined branch operation, the branch prediction logic being arranged to predict whether the predetermined branch operation will cause a change in instruction flow, in which event the branch prediction logic is arranged to indicate to the prefetch unit the target address determined by the target address logic. Accordingly, even though neither the first instruction nor the second instruction itself uniquely identifies the target address, the target address can nonetheless be uniquely determined thereby allowing prediction of the predetermined branch operation specified by the combination of the first and second instructions.

Abstract translation: 本发明提供一种用于预测数据处理装置中的分支指令的数据处理装置和方法。 数据处理装置包括用于执行指令的处理器，用于在将这些指令发送到处理器执行之前从存储器预取指令的预取单元，以及用于预测哪个指令应由预取单元预取的分支预测逻辑。 分支预测逻辑被布置为预测预取指令是否指定将导致指令流程改变的分支操作，并且如果是这样，则向预取单元指示应从其中检索下一指令的存储器内的目标地址。 指令包括可由处理器独立执行的第一指令和第二指令，它们组合指定预定的分支操作，其目标地址可以从第一和第二指令的属性的组合中唯一地导出。 数据处理装置还包括目标地址逻辑，用于从属性组合导出用于预定分支操作的目标地址，分支预测逻辑被布置为预测预定分支操作是否将引起指令流程的改变，在这种情况下 分支预测逻辑被布置为向预取单元指示由目标地址逻辑确定的目标地址。 因此，即使第一指令和第二指令本身都不唯一地识别目标地址，也可以唯一地确定目标地址，从而允许预测由第一和第二指令的组合指定的预定分支操作。

公开(公告)号：US06560692B1

公开(公告)日：2003-05-06

申请号：US08859490

申请日：1997-05-20

Applicant: Makoto Kudo ,  Satoshi Kubota ,  Yoshiyuki Miyayama ,  Hisao Sato

Inventor： Makoto Kudo ,  Satoshi Kubota ,  Yoshiyuki Miyayama ,  Hisao Sato

IPC: G06F1500

CPC classification number: G06F9/3004 ,  G06F9/30101 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/324 ,  G06F9/355

Abstract: The data processing circuit of this invention enables efficient description and execution of processes that act upon the stack pointer, using short instructions. It also enables efficient description of processes that save and restore the contents of registers, increasing the speed of processing of interrupts and subroutine calls and returns. A CPU that uses this data processing circuit comprises a dedicated stack pointer register SP and uses an instruction decoder to decode a group of dedicated stack pointer instructions that specify the SP as an implicit operand. This group of dedicated stack pointer instructions are implemented in hardware by using general-purpose registers, the PC, the SP, an address adder, an ALU, a PC incrementer, internal buses, internal signal lines, and external buses. This group of dedicated stack pointer instructions comprises SP-relative load instructions, stack pointer move instructions, a call instruction, a ret instruction, a sequential push instruction, and a sequential pop instruction.

Abstract translation: 本发明的数据处理电路能够使用简单的指令有效地描述和执行作用于堆栈指针的进程。 它还能够有效地描述保存和恢复寄存器内容的进程，提高处理中断和子程序调用和返回的速度。 使用该数据处理电路的CPU包括专用堆栈指针寄存器SP，并且使用指令解码器将指定SP的一组专用堆栈指针指令解码为隐式操作数。 该组专用堆栈指针指令通过使用通用寄存器，PC，SP，地址加法器，ALU，PC增量器，内部总线，内部信号线和外部总线在硬件中实现。 该组专用堆栈指针指令包括SP相对负载指令，堆栈指针移动指令，调用指令，ret指令，顺序推送指令和顺序pop指令。

公开(公告)号：US20030079105A1

公开(公告)日：2003-04-24

申请号：US10291617

申请日：2002-11-12

Inventor： Jonathan P. Douglas ,  Alan B. Kyker

IPC: G06F012/00

CPC classification number: G06F9/342 ,  G06F9/30167 ,  G06F9/324 ,  G06F9/3804

Abstract: A method of linear space target address generation for a relative branch is described. The method includes generating a selection signal, and generating a linear space target address using the selection signal by generating a plurality of corrected target addresses and selecting the linear space target address from the plurality of corrected target addresses using the selection signal.

公开(公告)号：US20020108029A1

公开(公告)日：2002-08-08

申请号：US10017198

申请日：2001-12-18

Inventor： Yuki Kondoh ,  Osamu Nishii

IPC: G06F009/00

CPC classification number: G06F9/382 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3802

Abstract: The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

Abstract translation: 本发明允许具有位移的PC相关分支指令的执行被加速而不改变现有处理器的指令操作，而不需要新的指令。 通过在将指令字存储在高速缓冲存储器或缓冲器中之前计算分支目标地址的下部，并将计算结果写入指令字的位移字段并将其写入已经被执行的位 添加到高速缓存或缓冲器中，使得通过使用存储在高速缓存或缓冲器中的执行的计算结果，在执行指令时稍后同时执行一些计算。

公开(公告)号：US20020078324A1

公开(公告)日：2002-06-20

申请号：US09928011

申请日：2001-08-10

Inventor： Holger Sedlak ,  Oliver Kniffler

IPC: H04L012/28 ,  G06F009/00

CPC classification number: G06F9/3822 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/321 ,  G06F9/324 ,  G06F9/3557

Abstract: A microprocessor for processing various assembler codes, in which a parameter that designates the respective assembler code is provided in the microprocessor and, in dependence on how the parameter is set, a different relative addressing takes place. A method of relative addressing in the microprocessor is also disclosed in which, dependent on an operating state or parameter for the respective assembler code, relative addresses are differently determined.

Abstract translation: 用于处理各种汇编代码的微处理器，其中在微处理器中提供指定各个汇编代码的参数，并且根据如何设置参数，发生不同的相对寻址。 还公开了一种在微处理器中进行相对寻址的方法，其中依赖于相应汇编代码的操作状态或参数，相对地址被不同地确定。

公开(公告)号：US20020032849A1

公开(公告)日：2002-03-14

申请号：US09802120

申请日：2001-03-08

Inventor： Ashley Saulsbury ,  Nyles Nettleton ,  Michael Parkin ,  David Emberson

IPC: G06F015/00

CPC classification number: G06F9/324 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30181 ,  G06F9/321 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3889

Abstract: According to the invention, a processing core (12) comprising a processing pipeline (100) having N-number of processing paths (56), each of which process instructions (54) on M-bit data words. In addition, the processing core (12) includes one or more register files (60), each preferably having Q-number of registers which are M-bits wide. Preferably, one of the Q-number of registers in at least one of the register files (60) is a program counter register dedicated to hold a program counter, and one of the Q-number of registers in at least one of the register files is a zero register dedicated to hold a zero value. In this manner, program jumps can be executed by adding values to the program counter in the program counter register, and memory address values can be calculated by adding values to the program counter stored in the program counter register or to the zero value stored in the zero register.

Abstract translation: 根据本发明，一种包括具有N个处理路径（56）的处理流水线（100）的处理核心（12），其中每个处理指令（54）在M位数据字上。 此外，处理核心（12）包括一个或多个寄存器文件（60），每个寄存器文件（60）优选地具有M位宽的寄存器的Q个数量。 优选地，至少一个寄存器文件（60）中的Q个寄存器之一是专用于保存程序计数器的程序计数器寄存器，并且至少一个寄存器堆栈中的一个寄存器中的一个 是一个专用于保持零值的零寄存器。 以这种方式，可以通过向程序计数器寄存器中的程序计数器添加值来执行程序跳转，并且可以通过将值附加到存储在程序计数器寄存器中的程序计数器或存储在程序计数器寄存器中的零值来计算存储器地址值 零寄存器

公开(公告)号：US06311263B1

公开(公告)日：2001-10-30

申请号：US08809498

申请日：1997-03-24

Applicant: Stephen John Barlow ,  Alistair Guy Morfey ,  James Digby Collier

Inventor： Stephen John Barlow ,  Alistair Guy Morfey ,  James Digby Collier

IPC: G06F13364

CPC classification number: G06F7/57 ,  G06F1/3203 ,  G06F1/3237 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/3005 ,  G06F9/30083 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3869 ,  G06F11/2236 ,  G06F11/3648 ,  G06F11/3656 ,  G06F15/7832 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analogue and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SER-CLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimize power consumption.

Abstract translation: 集成电路包含微处理器内核，程序存储器和单独的数据存储器，以及模拟和数字信号处理电路。 ALU为16位宽，但提供32位移位单元，使用一对16位寄存器。 处理器具有固定长度的指令格式，其中指令集包括在多个周期内使用移位单元的乘法和除法运算。 不提供中断。 集成电路的外部引脚允许单步和其他调试操作，以及允许外部通信测试数据或工作数据的串行接口（SIF）。 串行接口有四根线（SERIN，SEROUT，SER-CLK，SERLOADB），允许与主设备进行握手，并允许直接访问处理器内核的存储空间，无需特定的程序控制。 在每个处理器周期内，处理器电路被分成多个级，并且锁存器插在两个级之间以使功耗最小化。

公开(公告)号：US06272620B1

公开(公告)日：2001-08-07

申请号：US09543387

申请日：2000-04-04

Applicant: Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

Inventor： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC: G06F1500

CPC classification number: G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract translation: 采用通用寄存器方法的微型计算机MCU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点 通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。 并且，通过注意码位来执行编码除法的控制。

公开(公告)号：US06253308B1

公开(公告)日：2001-06-26

申请号：US09053638

申请日：1998-04-02

Applicant: Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

Inventor： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC: G06F1500

CPC classification number: G06F7/535 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3867 ,  G06F2207/5352

Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract translation: 采用通用寄存器方法的微型计算机CMU能够具有使用效率和低系统成本的小程序容量或高程序存储器，同时具有如在具有固定长度指令的RISC机器中简化指令解码的优点 通过采用固定长度指令格式，该格式具有功率为2但比为指令执行馈送的最大数据字长的位数小的固定长度指令格式。 并且，通过注意码位来执行编码除法的控制。

公开(公告)号：US06205535B1

公开(公告)日：2001-03-20

申请号：US09167029

申请日：1998-10-06

Applicant: Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

Inventor： Shumpei Kawasaki ,  Eiji Sakakibara ,  Kaoru Fukada ,  Takanaga Yamazaki ,  Yasushi Akao ,  Shiro Baba ,  Toshimasa Kihara ,  Keiichi Kurakazu ,  Takashi Tsukamoto ,  Shigeki Masumura ,  Yasuhiro Tawara ,  Yugo Kashiwagi ,  Shuya Fujita ,  Katsuhiko Ishida ,  Noriko Sawa ,  Yoichi Asano ,  Hideaki Chaki ,  Tadahiko Sugawara ,  Masahiro Kainaga ,  Kouki Noguchi ,  Mitsuru Watabe

IPC: G06F9/32

CPC classification number: G06F9/30036 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3802 ,  G06F9/3814

Abstract: A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Abstract translation: 分支指令格式对于条件分支指令和无条件分支指令具有不同的相应字段长度。 条件分支指令具有第一位长度和用于指定要跳转的地址的位移的第一区域，其中第一区域具有小于第一位长度的第二位长度。 无条件分支指令还具有第一位长度，以及用于指定要跳转的地址的位移的第二区域，其中第二区域具有不同于第一和第二位长度的第三位长度。