公开(公告)号：US5253195A

公开(公告)日：1993-10-12

申请号：US13541

申请日：1993-02-04

Applicant: Harold J. Broker ,  Russell S. Cook ,  James O'Connor ,  Nelson S. Xu

Inventor： Harold J. Broker ,  Russell S. Cook ,  James O'Connor ,  Nelson S. Xu

IPC: G06F7/50 ,  G06F7/52 ,  G06F11/00

CPC classification number: G06F7/5275 ,  G06F7/509 ,  G06F7/5338 ,  G06F2207/3844

Abstract: A high speed digital multiplier utilizes a variation in known shift-and-add algorithms. Each cycle, a single digit of the multiplier and the entire multiplicand are processed to form a "partial product" that is added to the result of the next cycle. The end result is a two part product, the high order product being generated by a carry-propagate adder, and the low order product being generated by a "spill adder" that produces one digit each cycle. Inputs of a carry-propagate adder are fed directly from outputs of a carry-save adder rather than running sum and carry registers. With a multiplier digit of 16-bits, a fixed point halfword multiply requires one execution cycle, a fixed point fullword multiply requires two execution cycles, and a floating point long multiply requires four execution cycles with additional overhead if pre- or post-normalization is required.

Abstract translation: 高速数字乘法器利用已知的移位和加法算法的变化。 每个周期，乘数和整个被乘数的单个数字被处理以形成添加到下一个周期的结果的“部分乘积”。 最终结果是两部分乘积，高阶乘积由进位传播加法器产生，低阶乘积由“溢出加法器”产生，每个周期产生一个数字。 进位传播加法器的输入直接从进位保存加法器的输出进给，而不是运行和和进位寄存器。 使用16位的乘数，固定点半字乘法需要一个执行周期，固定点全字乘法需要两个执行周期，如果前或后归一化后，浮点长乘法需要四个执行周期，额外的开销 需要。

公开(公告)号：US5218564A

公开(公告)日：1993-06-08

申请号：US712208

申请日：1991-06-07

Applicant: Ralph W. Haines ,  Gary D. Phillips ,  D. Kevin Covey ,  Thomas W. S. Thomson

Inventor： Ralph W. Haines ,  Gary D. Phillips ,  D. Kevin Covey ,  Thomas W. S. Thomson

IPC: G06F7/533 ,  G06F7/52 ,  G06F7/53 ,  G06F7/544 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F7/5338 ,  G06F7/5443 ,  G06F9/3877 ,  G06F2207/3876 ,  G06F7/4991 ,  G06F7/49921

Abstract: An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms. Instead of clearing the adder of the result of one multiplication before beginning another, the result is maintained and all subsequent partial products are added to it to generate a final output. The placement of the 32-bits of the multiply/accumulate unit's multiplicand register is arranged in two rows of 8 even bits and two rows of 8 odd bits to allow left shift by two with a single loop around and to provide direct interface with the 16-bit data latch register on its input and the rest of the 32-bit arithmetic logic unit (ALU) on its output.

公开(公告)号：US5181185A

公开(公告)日：1993-01-19

申请号：US638449

申请日：1991-01-04

Applicant: Tack D. Han ,  Sang M. Moh

Inventor： Tack D. Han ,  Sang M. Moh

IPC: G06F7/506 ,  G06F7/52 ,  G06F7/523 ,  G06F7/53 ,  G06F7/533

CPC classification number: G06F7/5318 ,  G06F7/533 ,  G06F7/5338 ,  G06F2207/3876

Abstract: A parallel multiplier by a skip array and a modified Wallace tree utilizes a modified Booth's encoder for encoding a multiplier according to a modified Booth's algorithm, a skip array for partial products, a modified wallace tree for adding binary bits, and a hybrid prefix adder for adding the final two lines. Fast multiplication of 0 (log n) is continuously performed without a standby state of a carry output and the regularity of the arrangement of the parallel multiplier is improved so that its chip area and manufacturing cost are reduced.

Abstract translation: 通过跳过阵列和修改的华莱士树，并行乘法器利用经修改的布斯编码器根据经修改的布斯算法，部分乘积的跳过阵列，用于添加二进制位的修改的华莱士树，以及混合前缀加法器 添加最后两行。 连续执行0（log n）的快速乘法，而没有进位输出的待机状态，并且提高了并行乘法器的布置的规则性，从而降低了其芯片面积和制造成本。

公开(公告)号：US4991131A

公开(公告)日：1991-02-05

申请号：US106493

申请日：1987-10-06

Applicant: I-Hau Yeh ,  Ye-O You ,  Wen-Zen Shen

Inventor： I-Hau Yeh ,  Ye-O You ,  Wen-Zen Shen

IPC: G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F7/74

CPC classification number: G06F7/74 ,  G06F7/4876 ,  G06F7/5443 ,  G06F7/5338

Abstract: A multiplication device is provided for forming the product of a first and a second N-bit input binary number. The multiplication device receives the two input binary numbers and forms a two's complement product expressed in a product sum and a product carry term. The product sum and product carry terms are formed by providing an offset generation means which generates a numerical binary offset of the value determined by X=(4-2.sup.-(n-1)) and a partial product generating means which generates first and second sets of partial products. An addition means adds the offset value and first and second sets of partial products are added to form the resultant product sum and product carry terms. The product sum and product carry terms are conveyed to a second addition means wherein they are added to form a two's complement product result. Preferably the multiplication device is provided with an accumulation means to form the sum of the products of all successive pairs of input binary numbers. In this manner, the second addition means also receives from a holding means an accumulation of previously formed products in two's complement form and adds the accumulation of products, the product sum and the product carry terms to form a new two's complement accumulation of products. The new accumulation of products is conveyed to the holding means where it replaces the old accumulation of products.

Abstract translation: 提供乘法装置，用于形成第一和第二N位输入二进制数的乘积。 乘法装置接收两个输入的二进制数，并形成以乘积和产品表示的二进制补码。 通过提供产生由X =（4-2-（n-1））确定的值的数字二进制偏移的偏移生成装置和产生第一和第二的部分乘积生成装置来形成乘积和乘积项 套部分产品。 加法装置增加偏移值，并且添加第一和第二组部分乘积以形成产生的乘积和乘积项。 产品总和和产品携带条件被传送到第二添加装置，其中它们被添加以形成二的补货产品结果。 优选地，乘法装置设置有累积装置，以形成所有连续输入二进制数对的乘积之和。 以这种方式，第二添加装置还从保持装置接收先前形成的产品的二次补码形式的积累，并且增加产品的积累，产品总和和产品携带条款以形成产品的新的二进制补码积分。 产品的新积累被传达到了取代旧产品积聚的手段。

公开(公告)号：US4853887A

公开(公告)日：1989-08-01

申请号：US95214

申请日：1987-09-11

Applicant: Francis Jutand ,  Nicolas Demassieux ,  Michel Dana

Inventor： Francis Jutand ,  Nicolas Demassieux ,  Michel Dana

IPC: G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53 ,  G06F7/533

CPC classification number: G06F7/5055 ,  G06F7/523 ,  G06F2207/3876 ,  G06F7/5338

Abstract: Binary adder having a fixed operand and a parallel-serial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.) are wired to incorporate the value of the fixed operand B. The non-fixed operand D is applied in serial form to the control input of a multiplexer. The multiplier also comprises an accumulator-shift register for storing a partial result A of the multiplication. As a function of the state of the multiplexer, the register receives A or A+B.

Abstract translation: 具有固定操作数的二进制加法器和并入这种加法器的并行串行二进制乘法器。 乘法器包括一个专用加法器，其元件（晶体管，逻辑门等）被连接以并入固定操作数B的值。非固定操作数D以串行形式施加到多路复用器的控制输入。 乘法器还包括用于存储乘法的部分结果A的累加器移位寄存器。 作为多路复用器状态的函数，寄存器接收A或A + B。

公开(公告)号：US4825401A

公开(公告)日：1989-04-25

申请号：US25201

申请日：1987-03-12

Applicant: Nobuyuki Ikumi

Inventor： Nobuyuki Ikumi

IPC: G06F7/533 ,  G06F7/507 ,  G06F7/508 ,  G06F7/52 ,  G06F7/53

CPC classification number: G06F7/5338 ,  G06F2207/3828

Abstract: A multiplier array circuit including decoders for decoding a multiplier on the basis of Booth's algorithm; cell array blocks for receiving the selection signals from the decoders and a multiplicand and performing the multiplication of the multiplicand and the multiplier on the basis of Booth's algorithm; and an adder for obtaining the final products on the basis of the outputs from the cell array blocks. In order to enable the functionally divisional operation, the cell array blocks includes complex cells which operate as the basic cells in the non-division mode and which operate as the code cells in the division mode. Further, the cell array blocks include selectors to supply an inactive value to the cells to perform the multiplication of the upper bits of the multiplicand and the lower bits of the multiplier and to the cells to perform the multiplication of the lower bits of the multiplicand and the upper bits of the multiplier in such a manner that the cell array blocks can supply the multiplicand and its inverted data to the cells constituting the cell array blocks in the non-division mode and can simultaneously execute two series of multiplications in the division mode.

公开(公告)号：US4755962A

公开(公告)日：1988-07-05

申请号：US45782

申请日：1987-04-29

Applicant: Yeshayahu Mor

Inventor： Yeshayahu Mor

IPC: G06F7/52

CPC classification number: G06F7/5338

Abstract: A modified Booth algorithm is implemented in the arithmetic logic of the ALU data path to cut the number of cycles to do a multiply in half thereby improving execution time of the multiplication operation. A Booth Encoder examines the two least significant bits of the multiplier stored in the Q2 register and the bit which was previously shifted out on the last partial product shift cycle. Based upon the status of these three bits, the Booth Encoder causes the ALU to add or substract one times the multiplicand to the contents of the partial product register and shift twice, add or substract two times the multiplicand to the contents of the partial product register and shift twice, or do nothing but shift twice. A pre ALU B shifter provides a single left shift of the multiplicand to provide the multiplication by two when same is necessary.

Abstract translation: 在ALU数据路径的算术逻辑中实现了一种改进的布斯算法，以减少乘法运算的次数，从而改善乘法运算的执行时间。 展位编码器检查存储在Q2寄存器中的乘法器的两个最低有效位，以及在最后一个部分乘积移位周期之前被移出的位。 根据这三个位的状态，Booth Encoder使ALU将被乘数的一倍增加或减去部分乘积寄存器的内容，并移位两次，将被乘数的两倍加上或减去部分乘积寄存器的内容 并转移两次，或者只做两次移动。 前置ALU B移位器提供被乘数的单个左移，以在需要时提供乘法2。

公开(公告)号：US4706211A

公开(公告)日：1987-11-10

申请号：US651155

申请日：1984-09-17

Applicant: Takao Yamazaki ,  Seiichiro Iwase

Inventor： Takao Yamazaki ,  Seiichiro Iwase

IPC: G06F7/533 ,  G06F7/507 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53

CPC classification number: G06F7/5338 ,  G06F2207/3884

Abstract: A digital multiplying circuit in a parallel multiplying circuit which can multiply an input which changes at a high data rate by the pipeline processing. A multiplicand is inputted to this circuit. Partial product signal generating circuits of the number corresponding to only the number of partial product signals which are needed are provided. The partial product signal generating circuits produce the partial product signals in accordance with the state of predetermined bits of a multiplier. Each partial product signal is added, thereby obtaining a multiplication output of the multiplicand. The pipeline processing is performed in the adding operation of each partial product signal. The multiplier and multiplicand are delayed. The predetermined partial product signal generating circuits are arranged immediately before the adders which need the partial product signals, thereby obtaining the partial product. With this digital multiplying circuit, the total number of bits of registers is reduced and the circuit scale is made small.

Abstract translation: 并行乘法电路中的数字乘法电路，其可以将通过流水线处理以高数据速率变化的输入相乘。 被乘数被输入到该电路。 提供了与仅需要的部分产品信号的数量对应的部分产品信号发生电路。 部分乘积信号发生电路根据乘法器的预定位的状态产生部分乘积信号。 添加每个部分乘积信号，从而获得被乘数的乘法输出。 在每个部分积信号的相加操作中执行流水线处理。 乘数和被乘数被延迟。 预定的部分乘积信号发生电路紧接在需要部分乘积信号的加法器之前，从而获得部分乘积。 利用该数字乘法电路，减少寄存器的总位数，使电路规模变小。

公开(公告)号：US4597053A

公开(公告)日：1986-06-24

申请号：US510102

申请日：1983-07-01

Applicant: George P. Chamberlin

Inventor： George P. Chamberlin

IPC: G06F7/52 ,  G06F7/544 ,  G06F9/30 ,  G06F9/302 ,  G06F7/02

CPC classification number: G06F7/5338 ,  G06F7/544 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30021 ,  G06F2207/3884 ,  G06F7/49921

Abstract: A two-pass Multiplier/Accumulator Circuit is provided which performs various arithmetic operations on operands contained within an X Register 10 (FIG. 1) and a Y Register 20 and places the result in an Accumulator Register 40. The arithmetic operations are carried out by passing the product of the operands successively through an array of adders in the Adder unit 34. Each adder adds an appropriate multiple of the contents of the X Register to the Accumulator 40 or to the output of the previous adder. The multiples are selected according to the contents of the Y Register.The X and Y Registers are fully buffered so that additional data transfers and functions may be performed while an arithmetic operation is in progress in a "pipeline" manner.The circuit is also capable of indicating the maximum or minimum value in a sequence of numbers in response to a single computer instruction to the circuit.

Abstract translation: 提供了一个双通乘法器/累加器电路，其对包含在X寄存器10（图1）和Y寄存器20中的操作数执行各种算术运算，并将结果存储在累加器寄存器40中。算术运算由 通过加法器单元34中的加法器阵列连续地传递操作数的乘积。每个加法器将X寄存器的内容的适当倍数与累加器40或前一加法器的输出相加。 根据Y寄存器的内容选择倍数。 X和Y寄存器被完全缓冲，以便在以“流水线”方式进行算术运算时可以执行额外的数据传输和功能。 该电路还能够响应于对电路的单个计算机指令来指示数字序列中的最大值或最小值。

公开(公告)号：US4071904A

公开(公告)日：1978-01-31

申请号：US756465

申请日：1977-01-03

Applicant: Homer Warner Miller

Inventor： Homer Warner Miller

IPC: G06F7/52

CPC classification number: G06F7/5338 ,  G06F2207/4806

Abstract: A multiple-generating register generates one of several possible multiples of a binary number which is input thereto depending upon the informational content of a 3-bit control signal. For each data stage there exists a data selector circuit, a master/slave circuit, and an output buffer circuit. The device can be configured as an inverting shift register for test and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.

Abstract translation: 多产生寄存器根据3位控制信号的信息内容产生输入到其中的二进制数的几个可能的倍数中的一个。 对于每个数据级，存在数据选择器电路，主/从电路和输出缓冲电路。 该器件可以配置为反相移位寄存器，用于测试和诊断目的。 该器件以电流模式逻辑实现，并且电路的一部分对差分电平信号进行操作，以提高操作速度和效率。