公开(公告)号：US20180356984A1

公开(公告)日：2018-12-13

申请号：US16044257

申请日：2018-07-24

申请人： Toshiba Memory Corporation

发明人： Hiroshi YAO ,  Shinichi KANNO ,  Kazuhiro FUKUTOMI

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0604 ,  G06F3/0634 ,  G06F3/0641 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7205

摘要： According to one embodiment, a memory system comprises a non-volatile semiconductor memory having a plurality of first storage areas, the first storage areas being capable of including one or more second storage areas, a plurality of third storage areas in which data is written in a first mode, and a plurality of fourth storage areas in which data is written in a second mode, the first mode being different from the second mode, and processing circuitry. The processing circuitry performs acquiring the one or more second storage areas from the plurality of first storage areas, selecting a plurality of storage areas from the plurality of third storage areas or from the plurality of fourth storage areas based on a rate of valid date in fifth storage area, the fifth storage area being the plurality of fourth storage areas, the rate of valid data in the fifth storage area being a rate of the total amount of valid data stored in the fifth storage area with respect to the total capacity of the fifth storage area, and writing the valid data stored in the selected plurality of storage areas in the acquired one or more second storage areas using the second mode.

公开(公告)号：US20180267827A1

公开(公告)日：2018-09-20

申请号：US15684848

申请日：2017-08-23

申请人： Toshiba Memory Corporation

发明人： Shinichi KANNO

IPC分类号： G06F9/46 ,  G06F3/06

CPC分类号： G06F9/463 ,  G06F1/263 ,  G06F1/30 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0688 ,  G11C2211/5641 ,  H04W52/02

摘要： An information processing device connectable to a plurality of storage devices includes a power source circuit configured to supply power from a backup power source to each of the plurality of storage devices in response to a power loss event, and a processor. The processor is configured to transmit, to each of the storage devices, a first instruction to save user data that have been transmitted to the storage device and have not been written in a non-volatile manner, in response to the power loss event, and transmit, to at least one of the storage devices, a second instruction to save updated address translation information that corresponds to the user data and has not been reflected in an address translation table, upon receiving a response indicating completion of saving the user data from each of the storage devices.

公开(公告)号：US20180076828A1

公开(公告)日：2018-03-15

申请号：US15441031

申请日：2017-02-23

申请人： Toshiba Memory Corporation

发明人： Shinichi KANNO

IPC分类号： H03M13/05 ,  G11C11/56 ,  G11C16/04 ,  H03M13/00

摘要： A storage device includes a nonvolatile memory and a controller. The controller is configured to generate coded data based on write data and an error correction code generated from the write data, determine whether or not to invert each bit of the coded data, based on a logical page position of the nonvolatile memory in which the write data are to be written and a value “0” or “1” of bits that are more populated in the coded data than bits having the other value of “1” and “0”, invert each bit of the coded data upon determining to invert, and write the non-inverted or inverted coded data into the logical page position of the nonvolatile memory. The logical page position is one of logical page positions including a lower page and an upper page.