公开(公告)号：US11062076B2

公开(公告)日：2021-07-13

申请号：US16997703

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Kai Hsu ,  Sheng-Hsiung Chen ,  Wai-Kei Mak ,  Ting-Chi Wang ,  Yu-Hsiang Cheng ,  Ding-Wei Huang

IPC: G06F30/392 ,  G06F30/398 ,  G03F1/70 ,  G06F30/31 ,  G06F111/04

Abstract: A method (of generating a layout diagram) includes: identifying, in the layout diagram, a group of three or more cells which violates a horizontal constraint vector (HCV) and is arranged so as to exhibit two or more vertically-aligned edge-pairs (VEPs); each VEP including two members representing at least partial portions of vertical edges of corresponding cells of the group; relative to a horizontal direction, the members of each VEP being disposed in edgewise-abutment and separated by a corresponding actual gap; and the HCV having separation thresholds, each of which has a corresponding VEP and represents a corresponding minimum gap in the horizontal direction between the members of the corresponding VEP; and for each of at least one but fewer than all of the separation thresholds, selectively moving a given one of cells corresponding to one of the members of the corresponding VEP thereby to avoid violating the HCV.

公开(公告)号：US11030372B2

公开(公告)日：2021-06-08

申请号：US16659351

申请日：2019-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pin-Dai Sue ,  Chin-Chou Liu ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Lee-Chung Lu ,  Yen-Hung Lin ,  Li-Chun Tien ,  Po-Hsiang Huang ,  Yi-Kan Cheng ,  Chi-Yu Lu

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

Abstract: A method (of generating a layout diagram) includes generating a cell, representing at least part of a circuit in a semiconductor device, which is arranged at least in part according to second tracks of the M_2nd level (M_2nd tracks), and first tracks of the M_1st level (M_1st tracks). The generating the cell includes: selecting, based on a chosen site for the cell in the layout diagram, one of the M_2nd tracks; generating a first M_2nd pin pattern representing an output pin of the circuit; arranging a long axis of the first pin pattern substantially along the selected M_2nd track; generating second, third, fourth and fifth M_1st pin patterns representing corresponding input pins of the circuit; and arranging long axes of the second to fifth pin patterns substantially along corresponding ones of the M_1st tracks.

公开(公告)号：US10977418B2

公开(公告)日：2021-04-13

申请号：US16579775

申请日：2019-09-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Ho Che Yu

IPC: H01L21/82 ,  H01L27/118 ,  G06F30/398 ,  G06F30/392 ,  H01L27/11575

Abstract: A semiconductor device including: first, second and third active regions a first gate structure over the first active region and a first part of the second active region; a second gate structure over the third active region and a second part of the second active region; a first cell region including the first gate structure, the first active region and the first part of the second active region; a second cell region including the second gate structure, the third active region and the second part of the second active region; a first border region representing an overlap of the first and second cell regions which is substantially aligned with an approximate midline of the second active region; the second gate structure overlapping the first border region; and there being a first gap which is between the first gate structure and the first border region.

公开(公告)号：US10262981B2

公开(公告)日：2019-04-16

申请号：US15465167

申请日：2017-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan Chang ,  Jyun-Hao Chang ,  Sheng-Hsiung Chen ,  Po-Hsiang Huang ,  Lipen Yuan

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/118

Abstract: A method of forming an integrated circuit is disclosed. The method includes generating, by a processor, a layout design of the integrated circuit, outputting the integrated circuit based on the layout design, and removing a portion of a conductive structure of the integrated circuit to form a first conductive structure and a second conductive structure. Generating the layout design includes generating a standard cell layout having a set of conductive feature layout patterns, placing a power layout pattern with the standard cell layout according to at least one design criterion, and extending at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to a boundary of the power layout pattern. The power layout pattern includes a cut feature layout pattern. The cut feature layout pattern identifies a location of the removed portion of the conductive structure of the integrated circuit.