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    STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION
    52.
    发明申请
    STRUCTURE AND METHOD TO FABRICATE pFETS WITH SUPERIOR GIDL BY LOCALIZING WORKFUNCTION 失效
    通过局部化工作来形成具有超级GIDL的结构和方法

    公开(公告)号：US20110215412A1

    公开(公告)日：2011-09-08

    申请号：US12717375

    申请日：2010-03-04

    申请人： Chengwen Pei ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

    发明人： Chengwen Pei ,  Roger A. Booth, JR. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/22

    CPC分类号： H01L21/22 ,  H01L21/8238 ,  H01L27/092

    摘要： A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.

    摘要翻译： 提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为 适应平带，但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。

    Shallow trench capacitor compatible with high-K / metal gate
    53.
    发明授权
    Shallow trench capacitor compatible with high-K / metal gate 有权
    浅沟槽电容器兼容高K /金属门

    公开(公告)号：US07875919B2

    公开(公告)日：2011-01-25

    申请号：US12059174

    申请日：2008-03-31

    申请人： Roger A. Booth, Jr. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

    发明人： Roger A. Booth, Jr. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

    IPC分类号： H01L27/108

    CPC分类号： H01L27/0629

    摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

    摘要翻译： 通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。 第二极性可以与第一极性相反。 额外的植入物可以减少第二细胞中的ESR。

    DYNAMIC RANDOM ACCESS MEMORY CELL INCLUDING AN ASYMMETRIC TRANSISTOR AND A COLUMNAR CAPACITOR
    54.
    发明申请
    DYNAMIC RANDOM ACCESS MEMORY CELL INCLUDING AN ASYMMETRIC TRANSISTOR AND A COLUMNAR CAPACITOR 有权
    动态随机存取存储器单元，包括不对称晶体管和柱型电容器

    公开(公告)号：US20100207179A1

    公开(公告)日：2010-08-19

    申请号：US12700807

    申请日：2010-02-05

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L21/823431 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10876 ,  H01L27/10879 ,  H01L28/60 ,  H01L29/66795 ,  H01L29/785

    摘要： A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.

    摘要翻译： 在衬底上形成具有第一导电类型掺杂的半导体鳍和半导体柱。 所述半导体柱和所述半导体鳍片的邻接端部掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂。 掺杂半导体柱构成电容器的内部电极。 在半导体鳍片和半导体柱上形成介电层和导电材料层。 图案化导电材料层以形成用于电容器的外部电极和栅电极。 可以进行单侧晕圈植入。 源极和漏极区域形成在半导体鳍片中以形成存取晶体管。 源极区域电连接到电容器的内部电极。 存取晶体管和电容器共同构成DRAM单元。

    Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode
    55.
    发明授权
    Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode 有权
    具有高k节点电介质和金属内电极的嵌入式沟槽电容器

    公开(公告)号：US07671394B2

    公开(公告)日：2010-03-02

    申请号：US11873728

    申请日：2007-10-17

    申请人： Roger A. Booth, Jr. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

    发明人： Roger A. Booth, Jr. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

    IPC分类号： H01L27/106 ,  H01L21/8242

    CPC分类号： H01L27/1087

    摘要： A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.

    摘要翻译： 在半导体衬底和衬垫层中形成深沟槽，并填充有虚拟节点电介质和虚设沟槽填充物。 在半导体衬底中形成浅沟槽隔离结构。 去除焊盘层之后，在器件区域中形成虚拟栅极结构。 在虚拟栅极结构上形成第一电介质层，并且填充虚拟沟槽的突出部分，然后进行平坦化。 虚拟结构被去除。 深沟槽和通过去除伪栅极结构形成的空腔填充有高介电常数材料层和金属层，其形成深沟槽中的高k节点电介质和深沟槽电容器的金属内电极 以及在器件区域中的高k栅极电介质和金属栅极。

    Semitubular metal-oxide-semiconductor field effect transistor
    57.
    发明授权
    Semitubular metal-oxide-semiconductor field effect transistor 有权
    半金属氧化物半导体场效应晶体管

    公开(公告)号：US07868374B2

    公开(公告)日：2011-01-11

    申请号：US12034899

    申请日：2008-02-21

    申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Jack A. Mandelman

    发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Jack A. Mandelman

    IPC分类号： H01L29/788

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7853

    摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.

    摘要翻译： 在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。 去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。 在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。 半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

    SOI CMOS compatible multiplanar capacitor
    58.
    发明授权
    SOI CMOS compatible multiplanar capacitor 有权
    SOI CMOS兼容多平面电容器

    公开(公告)号：US07728371B2

    公开(公告)日：2010-06-01

    申请号：US11857770

    申请日：2007-09-19

    申请人： Kangguo Cheng ,  Louis C Hsu ,  Jack A. Mandelman ,  William Tonti

    发明人： Kangguo Cheng ,  Louis C Hsu ,  Jack A. Mandelman ,  William Tonti

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/10861 ,  H01L28/60

    摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.

    摘要翻译： 孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。 环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。 隔离的浅沟槽隔离部分和由导电材料的环限定的掩​​埋绝缘体层的部分被蚀刻以形成空腔。 在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。 形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个 第二电极。

    Method of multi-port memory fabrication with parallel connected trench capacitors in a cell
    59.
    发明申请
    Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
    在单元中并联连接沟槽电容器的多端口存储器制造方法

    公开(公告)号：US20090176339A1

    公开(公告)日：2009-07-09

    申请号：US12316748

    申请日：2008-12-16

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jack A. Mandelman ,  Carl J. Radens ,  Geng Wang

    IPC分类号： H01L21/8242

    CPC分类号： G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

    摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.

    摘要翻译： 提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。 形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。 第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。 以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。