公开(公告)号：US10192280B2

公开(公告)日：2019-01-29

申请号：US15434851

申请日：2017-02-16

Applicant: QUALCOMM Incorporated

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Maurice Franklin Ribble ,  Andrew Evan Gruber

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: A graphics processing unit (GPU) may rasterize a primitive into a plurality of samples, wherein vertices of the primitive are associated with VRS parameters. The GPU may determine a VRS quality group that comprises one or more sub regions of the plurality of samples based at least in part on the VRS parameters. The GPU may fragment shade a VRS tile that represents the VRS quality group, wherein the VRS tile comprises fewer samples than the VRS quality group. The GPU may amplify the stored VRS tile into shaded fragments that correspond to the VRS quality group.

公开(公告)号：US09779534B2

公开(公告)日：2017-10-03

申请号：US14321409

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Usame Ceylan

IPC: G09G5/00 ,  G06T15/00 ,  G06T15/80 ,  G06T1/20 ,  G06T11/00 ,  G06T11/20 ,  G06T11/40 ,  G06T1/60 ,  G06T15/04 ,  G09G5/36

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/203 ,  G06T11/40 ,  G06T15/04 ,  G06T15/80 ,  G09G5/363

Abstract: In an example, rendering graphics data includes determining, with a graphics processing unit (GPU), a texture offset for a current segment of a plurality of ordered segments of a dashed line, where the texture offset for the current segment of the plurality of ordered segments is based on an accumulation of lengths of segments that precede the current segment in the order, and pixel shading the current segment including applying the texture offset to determine a location of the current segment.

公开(公告)号：US09679347B2

公开(公告)日：2017-06-13

申请号：US14182976

申请日：2014-02-18

Applicant: QUALCOMM Incorporated

Inventor： Chunhui Mei ,  Vineet Goel ,  Donghyun Kim

IPC: G06T1/00 ,  G06T1/60 ,  G06T15/80 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/005 ,  G06T15/80

Abstract: A graphics processing unit (GPU) may allocate a shared data channel in on-chip graphics memory of the GPU that is shared by at least two stages of a graphics processing pipeline. Shader units in the GPU may execute the at least two stages of the graphics processing pipeline. The GPU may store, in the shared data channel in on-chip graphics memory, data produced by each of the at least two stages of the graphics processing pipeline executing on the shader units.

公开(公告)号：US20160350892A1

公开(公告)日：2016-12-01

申请号：US14855962

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Gang Zhong ,  Vineet Goel ,  Young In Yeo ,  Juraj Obert

IPC: G06T1/20 ,  G06T15/80 ,  H04N13/04 ,  G06T15/00 ,  H04N13/02 ,  H04N13/00

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T15/80 ,  H04N13/106 ,  H04N13/139 ,  H04N13/261 ,  H04N13/275 ,  H04N13/30

Abstract: Techniques are described for stereoscopic view generation. A graphics processing unit (GPU) may combine attribute information for two or more corresponding vertices of corresponding primitives in different views. The GPU may process the combined attributed information to generate graphics data for the stereoscopic view.

Abstract translation: 描述了用于立体视图生成的技术。 图形处理单元（GPU）可以组合不同视图中对应图元的两个或多个对应顶点的属性信息。 GPU可以处理组合的归属信息以产生用于立体视图的图形数据。

公开(公告)号：US09483862B2

公开(公告)日：2016-11-01

申请号：US14137760

申请日：2013-12-20

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Usame Ceylan

IPC: G06T15/00 ,  G06T1/20 ,  G06T11/20

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T11/203 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) comprises a memory, and at least one processor configured to: receive a primitive type buffer comprising a plurality of primitive type entries, wherein each of a plurality of vertices of a vertex buffer of the GPU are associated with one or more of the plurality of primitive type entries, determine primitives based on the plurality of vertices and the associated one or more primitive type entries, and rendering, by the GPU, the primitives based on the plurality of vertices and the associated one or more primitive type entries of the primitive type buffer.

Abstract translation: 图形处理单元（GPU）包括存储器和至少一个处理器，其被配置为：接收包括多个基本类型条目的原语类型缓冲器，其中GPU的顶点缓冲器的多个顶点中的每一个与一个 多个基本类型条目中的多个或多个，基于多个顶点和相关联的一个或多个基本类型条目来确定原语，并且由GPU根据多个顶点和相关联的一个或多个原语渲染基元 键入基本类型缓冲区的条目。

公开(公告)号：US20160055667A1

公开(公告)日：2016-02-25

申请号：US14466554

申请日：2014-08-22

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Donghyun Kim ,  Gang Zhong

IPC: G06T15/83 ,  G06T15/00

CPC classification number: G06T15/83 ,  G06T15/005

Abstract: This disclosure describes techniques for executing shader programs in a graphics processing unit (GPU). In some examples, the techniques for executing shader programs may include executing, with a shader unit of a graphics processor, a shader program that performs vertex shader processing and that generates multiple output vertices for each input vertex that is received by the shader program. In further examples, the techniques for executing shader programs may include executing a merged vertex/geometry shader program using a non-replicated mode of execution. The non-replicated mode of execution may involve assigning each of a plurality of primitives to one merged vertex/geometry shader program instance per primitive and causing each of the instances to output a plurality of vertices. In additional examples, the techniques for executing shader programs may include techniques for selecting one of a non-replicated mode and a replicated mode for executing a merged vertex/geometry shader program.

Abstract translation: 本公开描述了用于在图形处理单元（GPU）中执行着色器程序的技术。 在一些示例中，用于执行着色器程序的技术可以包括使用图形处理器的着色器单元执行着色器程序，该着色器程序执行顶点着色器处理，并且为着色器程序接收的每个输入顶点生成多个输出顶点。 在另外的示例中，用于执行着色器程序的技术可以包括使用非复制的执行模式来执行合并的顶点/几何着色器程序。 非复制的执行模式可以包括将多个基元中的每一个分配给每个基元的一个合并的顶点/几何着色器程序实例，并使每个实例输出多个顶点。 在附加示例中，用于执行着色器程序的技术可以包括用于选择非复制模式和用于执行合并顶点/几何着色器程序的复制模式之一的技术。

公开(公告)号：US20150302629A1

公开(公告)日：2015-10-22

申请号：US14257385

申请日：2014-04-21

Applicant: QUALCOMM Incorporated

Inventor： Juraj Obert ,  Vineet Goel ,  Ouns Mouri

IPC: G06T15/06

CPC classification number: G06T15/06 ,  G06T2210/12

Abstract: At least one processor may organize a plurality of primitives in a hierarchical data structure. The at least one processor may rasterize a plurality of bounding volumes associated with non-root nodes of the hierarchical data structure to an off-screen render target. The at least one processor may determine a bounding volume that is intersected by a ray out of the plurality of bounding volumes. The at least one processor may determine a non-root node of the hierarchical data structure that is associated with the bounding volume as a start node in the hierarchical data structure to start traversal of the hierarchical data structure. The at least one processor may traverse the hierarchical data structure starting from the start node to determine the primitive that is intersected by the ray.

Abstract translation: 至少一个处理器可以在分层数据结构中组织多个基元。 所述至少一个处理器可以将与分层数据结构的非根节点相关联的多个边界卷光栅化为离屏渲染目标。 所述至少一个处理器可以确定由所述多个边界卷中的射线相交的边界体积。 所述至少一个处理器可以确定与所述分层数据结构相关联的所述分层数据结构的非根节点作为所述分层数据结构中的起始节点，以开始遍历所述分层数据结构。 至少一个处理器可以从开始节点开始遍历分层数据结构，以确定与射线相交的原语。

公开(公告)号：US20150294498A1

公开(公告)日：2015-10-15

申请号：US14686696

申请日：2015-04-14

Applicant: QUALCOMM Incorporated

Inventor： Chunhui Mei ,  Tao Wang ,  Young In Yeo ,  Vineet Goel

IPC: G06T15/80 ,  G06T7/00 ,  G06T1/60 ,  G06T17/10 ,  G06T1/20

CPC classification number: G06T7/70 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T15/005 ,  G06T15/80 ,  G06T2210/12

Abstract: Techniques are described for stochastic rasterization. A graphics processing unit (GPU) may discard samples of bounding polygons that together indicate movement of one or more primitives before a pixel shader process the samples. The GPU may leverage a stencil buffer and stencil test for discarding of such samples.

Abstract translation: 技术描述为随机光栅化。 图形处理单元（GPU）可以丢弃在像素着色器处理样本之前一起指示一个或多个图元的移动的边界多边形的样本。 GPU可以利用模板缓冲区和模板测试来丢弃这样的样本。

公开(公告)号：US20150178974A1

公开(公告)日：2015-06-25

申请号：US14137760

申请日：2013-12-20

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Usame Ceylan

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T11/203 ,  G06T2200/28

Abstract: A graphics processing unit (GPU) comprises a memory, and at least one processor configured to: receive a primitive type buffer comprising a plurality of primitive type entries, wherein each of a plurality of vertices of a vertex buffer of the GPU are associated with one or more of the plurality of primitive type entries, determine primitives based on the plurality of vertices and the associated one or more primitive type entries, and rendering, by the GPU, the primitives based on the plurality of vertices and the associated one or more primitive type entries of the primitive type buffer.

Abstract translation: 图形处理单元（GPU）包括存储器和至少一个处理器，其被配置为：接收包括多个基本类型条目的原语类型缓冲器，其中GPU的顶点缓冲器的多个顶点中的每一个与一个 多个基本类型条目中的多个或多个，基于多个顶点和相关联的一个或多个基本类型条目来确定原语，并且由GPU根据多个顶点和相关联的一个或多个原语渲染基元 键入基本类型缓冲区的条目。

公开(公告)号：US20140111513A1

公开(公告)日：2014-04-24

申请号：US13659675

申请日：2012-10-24

Applicant: QUALCOMM INCORPORATED

Inventor： Usame Ceylan ,  Vineet Goel

IPC: G06T17/20

CPC classification number: G06T17/20

Abstract: Systems and methods for a tessellation are described. These systems and methods may divide the domain into a plurality of portions, including a first portion. The systems and methods may also determine coordinates for vertices for a first set of shapes that reside within the first portion, wherein each shape of the first set of shapes includes at least one vertex on a first edge of the first portion. After determining coordinates for the vertices for the first set of shapes, the systems and methods may determine coordinates for vertices for a second set of shapes that reside within the first portion. Each shape of the second set of shapes shares at least one vertex with at least one shape of the first set of shapes and none of the shapes of the second set of shapes includes a vertex on the first edge of the first portion.

Abstract translation: 描述了细分的系统和方法。 这些系统和方法可以将域划分成多个部分，包括第一部分。 系统和方法还可以确定驻留在第一部分内的第一组形状的顶点的坐标，其中第一组形状的每个形状包括在第一部分的第一边缘上的至少一个顶点。 在确定第一组形状的顶点的坐标之后，系统和方法可以确定位于第一部分内的第二组形状的顶点的坐标。 第二组形状的每个形状与至少一个具有第一组形状的形状的至少一个顶点共享，并且第二组形状的形状的一个形状都不包括在第一部分的第一边缘上的顶点。