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    CLOCK LINE DRIVING FOR SINGLE-CYCLE DATA OVER CLOCK SIGNALING AND PRE-EMPTION REQUEST IN A MULTI-DROP BUS
    51.
    发明申请
    CLOCK LINE DRIVING FOR SINGLE-CYCLE DATA OVER CLOCK SIGNALING AND PRE-EMPTION REQUEST IN A MULTI-DROP BUS 审中-公开

    公开(公告)号：US20190171589A1

    公开(公告)日：2019-06-06

    申请号：US16167193

    申请日：2018-10-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/161 ,  G06F13/376 ,  G06F13/4291 ,  G06F2213/0008 ,  G06F2213/0064

    Abstract: Systems, methods, and apparatus are described that enable single-cycle pre-emption on a serial bus. An apparatus is coupled to a serial bus through a bus interface and includes a controller configured to provide a clock signal on the first line of the serial bus, transmit data on a second line of the serial bus in accordance with timing provided by the clock signal, cause the line driver to enter a high impedance state after transmitting a first edge in the clock signal while transmitting the data on the second line, detect a first pulse on the clock signal while the line driver is in the high impedance state, cause the line driver to exit the high impedance state prior to transmitting a second edge in the clock signal, and initiate bus arbitration after detecting the first pulse. The first edge and the second edge may transition in opposite directions.

    TECHNIQUE FOR RFFE AND SPMI REGISTER-0 WRITE DATAGRAM FUNCTIONAL EXTENSION
    52.
    发明申请
    TECHNIQUE FOR RFFE AND SPMI REGISTER-0 WRITE DATAGRAM FUNCTIONAL EXTENSION 审中-公开

    公开(公告)号：US20190163649A1

    公开(公告)日：2019-05-30

    申请号：US16155554

    申请日：2018-10-09

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Helena Deirdre O'SHEA ,  Richard Dominic WIETFELDT ,  ZhenQi CHEN

    IPC: G06F13/16 ,  G06F3/06

    Abstract: Systems, methods, and apparatus for functionally extending a capability of a write datagram for RFFE and SPMI devices are provided. A sending device sets a configuration register to indicate an operation mode of a write command and generates a command code field in the write command. A most significant bit of the command code field has a value of 1 and remaining bits of the command code field are defined based on the operation mode. The sending device further includes payload bytes in a payload field of the write command based on the operation mode and sends the write command to a receiver via a bus interface. The sending device may also set a page-address register to include a page-address to be used if page segmented access (PSA) is enabled for the write command and set the configuration register to indicate whether the PSA for the write command is enabled.

    HETEROGENEOUS VIRTUAL GENERAL-PURPOSE INPUT/OUTPUT
    53.
    发明申请
    HETEROGENEOUS VIRTUAL GENERAL-PURPOSE INPUT/OUTPUT 审中-公开

    公开(公告)号：US20190129881A1

    公开(公告)日：2019-05-02

    申请号：US16142419

    申请日：2018-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Richard Dominic WIETFELDT ,  Radu PITIGOI-ARON ,  Lalan Jee MISHRA

    IPC: G06F13/40 ,  G06F13/42 ,  G06F9/54

    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. An apparatus includes a serial bus, and an originating device and destination device coupled to the serial bus. The originating device may be configured to generate a first virtual GPIO packet that carries a payload representative of signaling state of physical GPIO in the originating device, generate a second virtual GPIO packet that carries a payload representative of an event generated by a processor in the originating device, and transmit the first and second virtual GPIO packets on the serial bus. The destination device may be configured to receive the second virtual GPIO packet from the serial bus, and communicate the event to a processor of the destination device or modify signaling state of physical GPIO in the destination device in accordance with the payload of the second virtual GPIO packet.

    LOW POWER PCIE
    54.
    发明申请
    LOW POWER PCIE 审中-公开

    公开(公告)号：US20190107882A1

    公开(公告)日：2019-04-11

    申请号：US16155824

    申请日：2018-10-09

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  James Lionel PANIAN ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD ,  Amit GIL ,  Shaul Yohai YIFRACH

    IPC: G06F1/32 ,  G06F13/10 ,  G06F13/40

    Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

    VIRTUAL CHANNEL INSTANTIATION OVER VGI/VGMI
    55.
    发明申请
    VIRTUAL CHANNEL INSTANTIATION OVER VGI/VGMI 审中-公开

    公开(公告)号：US20180359117A1

    公开(公告)日：2018-12-13

    申请号：US15992046

    申请日：2018-05-29

    Applicant: QUALCOMM Incorporated

    Inventor： Richard Dominic WIETFELDT ,  Lalan Jee MISHRA

    IPC: H04L12/54 ,  H04L12/935 ,  H04L5/00 ,  H04L29/06

    CPC classification number: H04L12/5601 ,  H04L5/0044 ,  H04L49/3081 ,  H04L63/0428 ,  H04L2012/563

    Abstract: In an aspect, an apparatus obtains a payload to be transmitted to a receiver device, obtains a virtual general-purpose input/output and messaging interface (VGMI) packet that includes at least the payload, a virtual channel identifier, and a function bit configured as a virtual channel marker bit to indicate that the VGMI packet includes the virtual channel identifier, wherein the virtual channel identifier indicates information associated with processing the payload, and transmits the VGMI packet to the receiver device. In another aspect, an apparatus receives a VGMI packet from a transmitter device, wherein the VGMI packet includes at least a payload and a virtual channel identifier, determines that the VGMI packet includes the virtual channel identifier based on a function bit configured as a virtual channel marker bit, wherein the virtual channel identifier indicates information associated with processing the payload, and processes the data based on the information.

    INPUT/OUTPUT DIRECTION DECODING IN MIXED VGPIO STATE EXCHANGE
    56.
    发明申请
    INPUT/OUTPUT DIRECTION DECODING IN MIXED VGPIO STATE EXCHANGE 审中-公开

    公开(公告)号：US20180329837A1

    公开(公告)日：2018-11-15

    申请号：US15950955

    申请日：2018-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee MISHRA ,  Richard Dominic WIETFELDT ,  Mohit Kishore PRASAD

    IPC: G06F13/10 ,  G06F13/20 ,  G06F13/42

    CPC classification number: G06F13/102 ,  G06F13/105 ,  G06F13/20 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0016

    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. A method performed at a transmitting device coupled to a communication link includes maintaining in a first register, a plurality of virtual general-purpose input/output (VGPIO) bits representing state of a one or more output GPIO pins at least one bit representative of state of an input GPIO pin of the first device, receiving first VGPIO state information directed to the first register, writing or refraining from writing a first set of bits of the first VGPIO state information to the first register based on the value of corresponding bits of a second register. The second set of bits may be directed to the one or more bits representative of state of output GPIO pins.

    SENSORS GLOBAL BUS
    58.
    发明申请
    SENSORS GLOBAL BUS 审中-公开

    公开(公告)号：US20180225253A1

    公开(公告)日：2018-08-09

    申请号：US15942385

    申请日：2018-03-30

    Applicant: QUALCOMM Incorporated

    Inventor： Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT ,  Douglas Wayne HOFFMAN

    IPC: G06F13/42

    Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A first command is transmitted to devices coupled to a serial bus operated in a first mode in accordance with a first protocol to cause the serial bus to be operated in a second mode. After communicating in accordance with a second protocol while the serial bus is operated in the second mode, a second command is transmitted to the plurality of devices in accordance with the first protocol to terminate the second mode. In the second mode, extra symbols inserted into a sequence of symbols transmitted on the serial bus prevent the occurrence of an unintended signaling state on the serial bus. Pulses transmitted on a wire of the serial bus in the second mode may have their duration limited such that a filter of a second device suppresses the limited-duration pulses.

    SENSORS GLOBAL BUS
    59.
    发明申请
    SENSORS GLOBAL BUS 审中-公开

    公开(公告)号：US20180052802A1

    公开(公告)日：2018-02-22

    申请号：US15685783

    申请日：2017-08-24

    Applicant: QUALCOMM Incorporated

    Inventor： Radu PITIGOI-ARON ,  Richard Dominic WIETFELDT ,  Douglas Wayne HOFFMAN

    IPC: G06F13/42

    Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A method includes transmitting a first command on a serial bus while operating in a first mode of operation, exchanging first data with the first device in accordance with a second protocol associated with the second mode of operation, and exchanging second data with the first device in accordance with the second protocol after the first period of time. The first command may be transmitted in accordance with a first protocol to cause a first device to operate in a second mode of operation. The first device may be idle for a first period of time after the first data has been exchanged.

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