公开(公告)号：US07781810B1

公开(公告)日：2010-08-24

申请号：US11538217

申请日：2006-10-03

申请人： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

发明人： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L29/72

CPC分类号： H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

摘要： A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.

摘要翻译： 一种装置包括鳍片，第一栅极和第二栅极。 第一门形成在鳍片的第一侧附近，并且包括具有第一厚度并且具有与鳍片的上表面基本共面的上表面的第一材料层。 所述第二浇口邻近所述翅片的与所述第一侧相对的第二侧形成，并且包括具有第二厚度并具有与所述翅片的上表面基本共面的上表面的第二材料层，其中所述第一厚度 并且第二厚度基本上等于翅片的高度。

公开(公告)号：US06995438B1

公开(公告)日：2006-02-07

申请号：US10674478

申请日：2003-10-01

申请人： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

发明人： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795

摘要： A semiconductor device includes a substrate and an insulating layer formed on the substrate. A conductive fin may be formed on the insulating layer. Fully silicided source and drain regions may be formed adjacent to the fin. A metal gate may be formed over a portion of the fin via a damascene process.

摘要翻译： 半导体器件包括衬底和形成在衬底上的绝缘层。 可以在绝缘层上形成导电翅片。 完全硅化的源极和漏极区域可以形成在鳍片附近。 可以通过镶嵌工艺在鳍的一部分上形成金属栅极。

公开(公告)号：US06984569B2

公开(公告)日：2006-01-10

申请号：US10642916

申请日：2003-08-18

申请人： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

发明人： Olov B. Karlsson ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic ,  Qi Xiang

IPC分类号： H01L21/8224

CPC分类号： H01L29/7842 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

公开(公告)号：US06982464B2

公开(公告)日：2006-01-03

申请号：US10975473

申请日：2004-10-29

申请人： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

发明人： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L29/72

CPC分类号： H01L29/785 ,  H01L21/3212 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681

摘要： A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

摘要翻译： FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。 半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

公开(公告)号：US06974983B1

公开(公告)日：2005-12-13

申请号：US10768660

申请日：2004-02-02

申请人： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

发明人： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/062

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by a channel stop layer.

摘要翻译： 半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。 第二源极区域，第二漏极区域和第二鳍状结构通过沟道阻挡层与第一源极区域，第一漏极区域和第一鳍片结构分离。

公开(公告)号：US06936882B1

公开(公告)日：2005-08-30

申请号：US10614001

申请日：2003-07-08

申请人： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

发明人： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L21/28097 ,  H01L21/823443 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

摘要： A semiconductor device includes a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer. The first device may include a first fin formed on the insulating layer, a first dielectric layer formed on the first fin, and a partially silicided gate formed over a portion of the first fin and the first dielectric layer. A second device also may be formed on the insulating layer. The second device may include a second fin formed on the insulating layer, a second dielectric layer formed on the second fin, and a fully silicided gate formed over a portion of the second fin and the second dielectric layer.

摘要翻译： 半导体器件包括衬底和形成在衬底上的绝缘层。 可以在绝缘层上形成第一器件。 第一器件可以包括形成在绝缘层上的第一鳍片，形成在第一鳍片上的第一电介质层和形成在第一鳍片和第一介电层的一部分上的部分硅化栅极。 也可以在绝缘层上形成第二器件。 第二器件可以包括形成在绝缘层上的第二鳍片，形成在第二鳍片上的第二介电层，以及形成在第二鳍片和第二介电层的一部分上的完全硅化栅极。

公开(公告)号：US06914277B1

公开(公告)日：2005-07-05

申请号：US10674400

申请日：2003-10-01

申请人： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

发明人： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by an insulating layer.

摘要翻译： 半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。 第二源极区域，第二漏极区域和第二鳍状结构通过绝缘层与第一源极区域，第一漏极区域和第一鳍片结构分离。

公开(公告)号：US20050056845A1

公开(公告)日：2005-03-17

申请号：US10975473

申请日：2004-10-29

申请人： Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

发明人： Krishnashree Achuthan ,  Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC分类号： H01L21/321 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/3212 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681

摘要： A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

摘要翻译： FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。 半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

公开(公告)号：US20050029603A1

公开(公告)日：2005-02-10

申请号：US10633504

申请日：2003-08-05

申请人： Bin Yu ,  Shibly Ahmed ,  Haihong Wang

发明人： Bin Yu ,  Shibly Ahmed ,  Haihong Wang

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66795

摘要： A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.

摘要翻译： 半导体器件可以包括衬底和形成在衬底上的绝缘层。 第一器件可以形成在绝缘层上，包括第一鳍片。 第一翅片可以形成在绝缘层上，并且可以具有第一翅片长宽比。 第二装置可以形成在绝缘层上，包括第二鳍片。 第二翅片可以形成在绝缘层上，并且可以具有与第一翅片长宽比不同的第二翅片长宽比。

公开(公告)号：US06833588B2

公开(公告)日：2004-12-21

申请号：US10274867

申请日：2002-10-22

申请人： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

发明人： Bin Yu ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic ,  Haihong Wang

IPC分类号： H01L2701

CPC分类号： H01L29/785 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66803

摘要： A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.