公开(公告)号：US20240193922A1

公开(公告)日：2024-06-13

申请号：US18587869

申请日：2024-02-26

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM ,  Sun Mi LEE ,  Il Myeong IM

IPC: G06V10/776 ,  G06V10/24 ,  G06V10/82

CPC classification number: G06V10/776 ,  G06V10/24 ,  G06V10/82

Abstract: A control method of an image signal processor for an artificial neural network may be configured to include a step of acquiring an image, a step of determining at least one image characteristic data corresponding to the image, and a step of determining an image correction parameter (SFR preset) for improving an inference accuracy of an artificial neural network model based on the at least one of image characteristic data and an inference accuracy profile of an artificial neural network model.

公开(公告)号：US20230360719A1

公开(公告)日：2023-11-09

申请号：US18193313

申请日：2023-03-30

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM ,  Jeong Kyun YIM

IPC: G11C29/00 ,  G11C29/10

CPC classification number: G11C29/78 ,  G11C29/10

Abstract: A neural processing unit (NPU) for testing a component during runtime is provided. The NPU may include a plurality of functional components including a first functional component and a second functional component. At least one of the plurality of functional components may be driven for calculation of an artificial neural network. Another one of the plurality of functional components may be selected as a component under test (CUT). A scan test may be performed on the at least one functional component selected as the CUT. A tester for detecting a defect of an NPU is also provided. The tester may include a component tester configured to communicate with at least one functional component of the NPU, select the at least one functional component as a CUT, and perform a scan test for the selected CUT.

公开(公告)号：US20230359877A1

公开(公告)日：2023-11-09

申请号：US18353404

申请日：2023-07-17

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM ,  Jung Boo PARK ,  Seong Jin LEE

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.

公开(公告)号：US20230359180A1

公开(公告)日：2023-11-09

申请号：US17849667

申请日：2022-06-26

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM ,  Jeong Kyun YIM

IPC: G05B19/418

CPC classification number: G05B19/41875 ,  G05B2219/32368 ,  G05B2219/45031

Abstract: A neural processing unit (NPU) is capable of testing a component of the NPU in a running system, i.e., during runtime. The NPU includes a plurality of functional components, each of which includes an electronic circuit; at least one wrapper connected to at least one of the functional components; and an in-system component tester (ICT). The ICT performs a selection of one of the at least one functional component, in an idle state, as a component under test (CUT) and performs a test, via the at least one wrapper, of the selected functional component. The ICT may monitor states of the plurality of the functional components via the at least one wrapper, stop the test based on a detection of a collision due to an access to the selected functional component, and return a connection of the selected functional component to the at least one wrapper according to the stop.

公开(公告)号：US20220348229A1

公开(公告)日：2022-11-03

申请号：US17719359

申请日：2022-04-12

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM

IPC: B60W60/00 ,  G05B13/02 ,  B60W50/00

Abstract: A neural processing unit (NPU) includes a controller including a scheduler, the controller configured to receive from a compiler a machine code of an artificial neural network (ANN) including a fusion ANN, the machine code including data locality information of the fusion ANN, and receive heterogeneous sensor data from a plurality of sensors corresponding to the fusion ANN; at least one processing element configured to perform fusion operations of the fusion ANN including a convolution operation and at least one special function operation; a special function unit (SFU) configured to perform a special function operation of the fusion ANN; and an on-chip memory configured to store operation data of the fusion ANN, wherein the schedular is configured to control the at least one processing element and the on-chip memory such that all operations of the fusion ANN are processed in a predetermined sequence according to the data locality information.

公开(公告)号：US20220207336A1

公开(公告)日：2022-06-30

申请号：US17498766

申请日：2021-10-12

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM

IPC: G06N3/063 ,  G06N20/10

Abstract: A neural processing unit (NPU), a method for driving an artificial neural network (ANN) model, and an ANN driving apparatus are provided. The NPU includes a semiconductor circuit that includes at least one processing element (PE) configured to process an operation of an artificial neural network (ANN) model; and at least one memory configurable to store a first kernel and a first kernel filter. The NPU is configured to generate a first modulation kernel based on the first kernel and the first kernel filter and to generate second modulation kernel based on the first kernel and a second kernel filter generated by applying a mathematical function to the first kernel filter. Power consumption and memory read time are both reduced by decreasing the data size of a kernel read from a separate memory to an artificial neural network processor and/or by decreasing the number of memory read requests.

公开(公告)号：US20220137866A1

公开(公告)日：2022-05-05

申请号：US17512568

申请日：2021-10-27

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM

IPC: G06F3/06 ,  G06N3/063

Abstract: A memory device for an artificial neural network (ANN) includes at least one memory cell array of N columns and M rows; and a memory controller configured to sequentially perform a read or write operation of data of the at least one memory cell array in a burst mode based on predetermined sequential access information. Each of the at least one memory cell array may include a plurality of dynamic memory cells having a leakage current characteristic. The memory device may further include a processor configured to provide the memory controller with the ANN data locality information or information for identifying an input feature map, a kernel, and an output feature map. The memory controller can prepare data of an ANN model processed at a processor-memory level before being requested by the processor, thus enabling a substantial reduction in the delay of memory data being supplied to the processor.

公开(公告)号：US20210373646A1

公开(公告)日：2021-12-02

申请号：US17366042

申请日：2021-07-02

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM

IPC: G06F1/3287 ,  G06F1/3206 ,  G06K9/62 ,  G06N3/08

Abstract: A learning model creation method for performing a specific function for an electronic device, according to an embodiment of the present invention, can include the steps of: preparing big data for training an artificial neural network including, in pairs, sensing data received from a random sensing data generation unit for sensing human behaviors and specific function performance determination data for determining whether to perform a specific function of an electronic device with respect to the sensing data; preparing an artificial neural network model, which includes nodes of an input layer through which the sensing data is inputted, nodes of an output layer through which the specific function performance determination data of the electronic device is outputted, and association parameters between the nodes of the input layer and the nodes of the output layer, and calculates inputs of the sensing data for the nodes of the input layer in order to output the specific function performance determination data from the nodes of the output layer; and repeatedly performing a process of inputting the sensing data included in the prepared big data into the nodes of the input layer and outputting the specific function performance determination data that pairs with the sensing data included in the big data from the nodes of the output layer so as to update the association parameters, thereby mechanically training the artificial neural network model.

公开(公告)号：US20210150352A1

公开(公告)日：2021-05-20

申请号：US17135655

申请日：2020-12-28

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Disclosed is a data cache or data management device for caching data between at least one processor and at least one memory, and supporting an artificial neural network (ANN) operation executed by the at least one processor. The data cache device or the data management device can comprise an internal controller for predicting the next data operation request on the basis of ANN data locality of the ANN operation. The internal controller monitors data operation requests associated with the ANN operation from among data operation requests actually made between the at least one processor and the at least one memory, thereby extracting the ANN data locality of the ANN operation.

公开(公告)号：US20250165409A1

公开(公告)日：2025-05-22

申请号：US19032487

申请日：2025-01-21

Applicant: DEEPX CO., LTD.

Inventor： Lok Won KIM

IPC: G06F13/16 ,  G06F13/18

Abstract: An artificial neural network memory system includes at least one processor configured to generate a data access request corresponding to an artificial neural network operation; and at least one artificial neural network memory controller configured to sequentially record the data access request to generate an artificial neural network data locality pattern of the artificial neural network operation and generate an advance data access request which predicts a next data access request of the data access request generated by the at least one processor based on the artificial neural network data locality pattern.