公开(公告)号：US08464201B2

公开(公告)日：2013-06-11

申请号：US13441849

申请日：2012-04-07

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou ,  Shin-Ting Yen

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou ,  Shin-Ting Yen

IPC: G06F17/50 ,  G06G7/62

CPC classification number: G06F17/5036 ,  G06F2217/78

Abstract: An electronic device reads a layout file of a printed circuit board (PCB) to be manufactured from a storage device, obtains length information and section area information of copper cladding distributed on power source areas and ground trace areas in each of one or more layers of the PCB to be manufactured by analyzing the layout file, and calculates power loss in each of the one or more layers according to the length information, the section area information, a resistance value of the copper cladding, and preset parameters of a power supply module and an integrated circuit (IC) load to be located on the PCB. In response to a determination that the power loss in the layer exceeds a preset range, the electronic device indicates the locations of the power source areas and the ground trace areas of a layer in the PCB layout file which need to be redesigned.

Abstract translation: 电子设备读取要从存储装置制造的印刷电路板（PCB）的布局文件，获得在一个或多个层中的每一个中的电源区域和地面迹线区域上分布的铜包层的长度信息和截面面积信息 通过分析布局文件来制造PCB，并且根据长度信息，截面面积信息，铜包层的电阻值和电源模块的预设参数来计算一个或多个层中的每一个中的功率损耗 以及位于PCB上的集成电路（IC）负载。 响应于层中的功率损耗超过预设范围的确定，电子设备指示需要重新设计的PCB布局文件中的层的电源区域和地面迹线区域的位置。

公开(公告)号：US08451615B2

公开(公告)日：2013-05-28

申请号：US13087488

申请日：2011-04-15

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

IPC: H05K7/00

CPC classification number: H05K7/00 ,  H05K1/0201 ,  H05K1/0265 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0979

Abstract: A printed circuit board includes a top layer and a bottom layer. A power supply and an electronic component are located on the top layer. The power supply is connected to the top layer and the bottom layer through a first via. A number of second vias extends through the top layer and the bottom layer, and is electrically connected to the top layer and the bottom layer. A right-angled triangular void area without vias defined therein is formed on the printed circuit board, between the second vias and the electronic component. The second vias are arranged on a hypotenuse of the void area.

Abstract translation: 印刷电路板包括顶层和底层。 电源和电子元件位于顶层。 电源通过第一通孔连接到顶层和底层。 多个第二通孔延伸穿过顶层和底层，并且电连接到顶层和底层。 在印刷电路板上，在第二通孔和电子部件之间形成没有限定在其中的通孔的直角三角形空隙区域。 第二个通孔布置在空隙区域的斜边上。

公开(公告)号：US08436681B2

公开(公告)日：2013-05-07

申请号：US13008037

申请日：2011-01-18

Applicant: Duen-Yi Ho ,  Chun-Jen Chen ,  Wei-Chieh Chou ,  Tsung-Sheng Huang

Inventor： Duen-Yi Ho ,  Chun-Jen Chen ,  Wei-Chieh Chou ,  Tsung-Sheng Huang

IPC: G05F1/40

CPC classification number: H02M3/156 ,  H02M2001/0009

Abstract: A voltage regulating circuit includes a pulse width modulation controller, a current sense circuit, a voltage feedback circuit, and a gain-and-bias circuit. The current sense circuit includes an inductor and a capacitor. The voltage feedback circuit includes first and second resistors. The gain-and-bias circuit includes an operational amplifier. A first terminal of the capacitor is connected to an inverting input terminal of the operational amplifier through a third resistor. A second terminal of the capacitor is connected to a non-inverting input terminal of the operational amplifier through a fourth resistor. The inverting input terminal of the amplifier is connected to an output terminal of the operational amplifier through a fifth resistor. The non-inverting input terminal of the operational amplifier is grounded through a sixth resistor. The output terminal of the operational amplifier is connected to the node between the first and second resistors through a seventh resistor.

Abstract translation: 电压调节电路包括脉宽调制控制器，电流检测电路，电压反馈电路和增益与偏置电路。 电流检测电路包括电感器和电容器。 电压反馈电路包括第一和第二电阻器。 增益和偏置电路包括运算放大器。 电容器的第一端子通过第三电阻器连接到运算放大器的反相输入端子。 电容器的第二端子通过第四电阻器连接到运算放大器的非反相输入端子。 放大器的反相输入端通过第五个电阻连接到运算放大器的输出端。 运算放大器的非反相输入端通过第六个电阻接地。 运算放大器的输出端通过第七电阻连接到第一和第二电阻之间的节点。

公开(公告)号：US08283571B2

公开(公告)日：2012-10-09

申请号：US12790883

申请日：2010-05-31

Applicant: Ying-Tso Lai ,  Yung-Chieh Chen ,  Chun-Jen Chen ,  Wei-Chieh Chou

Inventor： Ying-Tso Lai ,  Yung-Chieh Chen ,  Chun-Jen Chen ,  Wei-Chieh Chou

IPC: H05K1/11

CPC classification number: H05K1/0225 ,  H05K1/0245 ,  H05K1/0253

Abstract: A printed circuit board includes a signal layer, a dielectric layer, and a reference layer. The signal layer includes a pair of differential signal lines. The dielectric layer is sandwiched between the signal layer and the reference layer. A first void is defined in the reference layer between projections of the pair of differential signal lines. Two second voids are defined in the reference layer at opposite sides of the projections of the pair of differential signal lines.

Abstract translation: 印刷电路板包括信号层，电介质层和参考层。 信号层包括一对差分信号线。 电介质层夹在信号层和参考层之间。 在该对差分信号线的投影之间的参考层中限定第一空隙。 在该对差分信号线的突起的相对侧的参考层中限定两个第二空隙。

公开(公告)号：US08013255B2

公开(公告)日：2011-09-06

申请号：US12126748

申请日：2008-05-23

Applicant: Shou-Kuo Hsu ,  Chun-Jen Chen

Inventor： Shou-Kuo Hsu ,  Chun-Jen Chen

IPC: H05K1/03

CPC classification number: H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336

Abstract: An exemplary PCB includes a first reference layer, a first signal layer, and a second signal layer in that order. A first differential pair is arranged in the first signal layer in an edge-coupled structure referencing the first reference layer. A second differential pair is arranged in the second signal layer in edge-coupled structure. A first ground part and a second ground part are symmetrically arranged in the second signal layer and at opposite sides of the second differential pair. The first differential pair is arranged above the first ground part such that a projection of the first differential pair onto the second signal layer having an area coincident with the first ground part. The second differential pair references the first and second ground parts.

Abstract translation: 示例性的PCB包括第一参考层，第一信号层和第二信号层。 第一差分对以参考第一参考层的边缘耦合结构布置在第一信号层中。 第二差分对以边缘耦合结构布置在第二信号层中。 第一接地部分和第二接地部分对称地布置在第二信号层中并且在第二差分对的相对侧。 第一差分对被布置在第一接地部分上方，使得第一差分对的突起与第一接地部分重合的区域的第二信号层上。 第二差分对参考第一和第二接地部分。

公开(公告)号：US07994656B2

公开(公告)日：2011-08-09

申请号：US12551463

申请日：2009-08-31

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho

IPC: H02J1/00

CPC classification number: G06F1/26 ,  G06F17/50 ,  H02J1/00 ,  Y10T307/25 ,  Y10T307/555

Abstract: A power supply system includes a power supply, a daughterboard, and a motherboard. Output currents of power connectors of the motherboard and impedances of copper foils between every two adjacent power connectors of the motherboard are obtained via simulation. A voltage of one power connector of the motherboard is predetermined. Therefore, desired impedances of copper foils between VRM connectors and corresponding power connectors on the daughter board are determined via calculations, to make currents passing through the power connectors of the motherboard equal to each other.

Abstract translation: 电源系统包括电源，子板和主板。 母板电源连接器的输出电流和母板每两个相邻电源连接器之间铜箔的阻抗通过仿真获得。 母板的一个电源连接器的电压是预先确定的。 因此，通过计算确定VRM连接器与子板上相应的电源连接器之间的铜箔的期望阻抗，以使通过主板的电源连接器的电流彼此相等。

公开(公告)号：US20110159410A1

公开(公告)日：2011-06-30

申请号：US12650985

申请日：2009-12-31

Applicant: Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

Inventor： Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

IPC: G03F1/00 ,  G06F17/50

CPC classification number: G03F1/24 ,  G03F1/72 ,  G03F1/84

Abstract: The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping.

Abstract translation: 本公开提供了许多不同的实施例。 示例性方法可以包括提供空白掩模和要在空白掩模上图案化的设计布局，所述设计布局包括临界区域; 检查空白掩模的缺陷并产生与空白掩模相关联的缺陷分布图; 将缺陷分布图映射到设计布局; 进行面膜制作过程; 以及基于所述映射执行掩模缺陷修复处理。

公开(公告)号：US07940127B2

公开(公告)日：2011-05-10

申请号：US12330100

申请日：2008-12-08

Applicant: Huan-Ke Chiu ,  Chun-Jen Chen

Inventor： Huan-Ke Chiu ,  Chun-Jen Chen

IPC: H03L7/085

CPC classification number: H03L7/107 ,  H03L7/0991 ,  H03L7/10 ,  H03L7/1806 ,  H03L2207/50

Abstract: An all digital phase lock loop is disclosed, including a digitally controlled oscillator, a phase detector, and a loop filter. The digitally controlled oscillator is controlled by an oscillator tuning word to generate a variable signal. The oscillator tuning word includes a first tuning word and a second tuning word, where the frequency range of the digitally controlled oscillator, capable to be adjusted by the second tuning word, is broader than that capable to be adjusted by the first tuning word. The phase detector detects a phase error between the variable signal and a reference signal. The phase error is received by the loop filter to output the oscillator tuning word. The loop filter has several stages of the low pass filters and a modification circuit. The modification circuit detects two filter outputs from two low pass filters among the filters and accordingly adjusts the second tuning word.

Abstract translation: 公开了一种全数字锁相环，包括数字控制振荡器，相位检测器和环路滤波器。 数字控制振荡器由振荡器调谐字控制，以产生可变信号。 振荡器调谐字包括第一调谐字和第二调谐字，其中能够由第二调谐字调节的数字控制振荡器的频率范围比能够被第一调谐字调整的频率范围宽。 相位检测器检测可变信号和参考信号之间的相位误差。 相位误差由环路滤波器接收以输出振荡器调谐字。 环路滤波器具有几级低通滤波器和修改电路。 修改电路检测滤波器中的两个低通滤波器的两个滤波器输​​出，并相应地调整第二个调谐字。

公开(公告)号：US07791429B2

公开(公告)日：2010-09-07

申请号：US12168541

申请日：2008-07-07

Applicant: Chun-Jen Chen ,  Shou-Kuo Hsu

Inventor： Chun-Jen Chen ,  Shou-Kuo Hsu

IPC: H03H7/03 ,  H04B3/04

CPC classification number: H04L27/01 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10189

Abstract: An equalizer includes a first resistor and a capacitor connected in parallel. The positive terminal of the capacitor is connected to a signal transmission line on a blah printed circuit board. The negative terminal of the capacitor is connected to ground through a second resistor. A connector including the equalizer and a printed circuit board including the connector are also provided.

Abstract translation: 均衡器包括并联连接的第一电阻器和电容器。 电容器的正极端子连接到blah印刷电路板上的信号传输线。 电容器的负极通过第二个电阻连接到地。 还提供了包括均衡器的连接器和包括连接器的印刷电路板。

公开(公告)号：US07657564B2

公开(公告)日：2010-02-02

申请号：US11525445

申请日：2006-09-22

Applicant: Shou-Kuo Hsu ,  Chun-Jen Chen ,  Chun-Shan Hsiao

Inventor： Shou-Kuo Hsu ,  Chun-Jen Chen ,  Chun-Shan Hsiao

IPC: G06F17/30

CPC classification number: H03H1/0007 ,  H03H2260/00

Abstract: A method for selecting a ferrite bead for a filter to avoid a peak value in a frequency response curve of the filter is provided. The method includes the steps of: building an equivalent model database including parameters of equivalent models of ferrite beads, the parameters including an inductance and a capacitance of a corresponding equivalent model of each ferrite bead; calculating parameters of a desired ferrite bead in the filter based on parameters of the filter, the parameters of the ferrite bead including an inductance, a capacitance, and a resonant frequency; adjusting parameters of the filter until the calculated resonant frequency equals or approaches a desired resonant frequency, and finding an inductance and a capacitance respectively equaling or approaching the calculated inductance and the calculated capacitance in the database; and selecting a ferrite bead with the appropriate inductance and capacitance as found in the database for the filter.

Abstract translation: 提供了一种用于选择用于滤波器的铁氧体磁珠以避免滤波器的频率响应曲线中的峰值的方法。 该方法包括以下步骤：构建等效模型数据库，其中包括铁素体磁珠的等效模型参数，其参数包括每个铁氧体磁珠的相应等效模型的电感和电容; 基于滤波器的参数，包括电感，电容和谐振频率的铁氧体磁珠的参数来计算滤波器中期望的铁氧体磁珠的参数; 调整滤波器的参数，直到计算出的谐振频率等于或接近期望的谐振频率，并且找到分别等于或接近计算出的电感的电感和电容以及数据库中的计算电容; 并选择具有适当的电感和电容的铁氧体磁珠，如过滤器数据库中所述。