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公开(公告)号：US20140168782A1
公开(公告)日：2014-06-19
申请号：US14102248
申请日：2013-12-10
Inventor： Rong Tang , Xiang Li , Bin Zou , Dan Wang , Xibin Shao
IPC: G02B3/00
CPC classification number: G02B3/0056 , G02F1/133611 , G02F2001/133607
Abstract: A brightness enhancement film includes a substrate; and a microlens structure formed on the substrate, wherein the microlens structure comprises a plurality of microlenses, each of the microlenses comprising a bottom surface contacting with the substrate, the bottom surface of each of the plurality of microlenses being of a polygonal shape such that at the substrate each of the plurality of microlenses is in close contact with adjacent microlenses surrounding it, without gaps leaving between them. The present invention also discloses a backlight module and a display apparatus comprising the above brightness enhancement film. The brightness enhancement film can improve optical gain property, reduce the thickness of the display apparatus and expand the view angle.
Abstract translation: 亮度增强膜包括基板; 以及形成在所述衬底上的微透镜结构，其中所述微透镜结构包括多个微透镜，所述微透镜中的每一个包括与所述衬底接触的底表面，所述多个微透镜中的每一个的底表面为多边形形状， 多个微透镜中的每个基板与其周围的相邻微透镜紧密接触，而在它们之间没有间隙。 本发明还公开了一种背光模块和包括上述增亮膜的显示装置。 亮度增强膜可以提高光学增益特性，减小显示装置的厚度并扩大视角。
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公开(公告)号：US12236912B2
公开(公告)日：2025-02-25
申请号：US17915712
申请日：2021-10-28
Inventor： Yanping Liao , Yingmeng Miao , Seungmin Lee , Xibin Shao , Shulin Yao , Yinlong Zhang , Qiujie Su , Cong Wang , Dongchuan Chen , Jiantao Liu
IPC: G09G3/36 , G09G3/3266 , G11C19/28
Abstract: A display panel, a driving method for the display panel and a display device. The display panel includes a gate driving circuit, the gate driving circuit includes shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively; an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)th stage that are cascaded, where m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, N is an even number that is greater than or equal to 2.
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公开(公告)号：US12218149B2
公开(公告)日：2025-02-04
申请号：US17637893
申请日：2021-04-27
Inventor： Cong Wang , Yingmeng Miao , Dongchuan Chen , Seungmin Lee , Yanping Liao , Xibin Shao , Jiantao Liu
IPC: G02F1/1362 , G02F1/1333 , G02F1/1339 , G02F1/1343 , G02F1/1368 , H01L27/12
Abstract: A dual gate array substrate includes a plurality of groups of dual gate lines, a plurality of data lines, a plurality of pixel pairs and a plurality of common electrode lines, each common electrode line is arranged between two pixel units in a same pixel pair; and a layer where the common electrode line is located and a layer where a source/drain electrode of a thin film transistor is located are different layers and insulated from each other.
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54.发明授权公开(公告)号：US12175949B2
公开(公告)日：2024-12-24
申请号：US17913430
申请日：2021-11-10
Inventor： Jianting Wang , Xibin Shao , Changjia Fu
Abstract: A color coordinate calibration method, system, a processing device and a computer storage medium are provided. The method includes: displaying a test image on a display screen, testing the chromaticity of the display screen, and obtaining test color coordinates of a plurality of primary color lights; Detecting whether the test color coordinates of the plurality of primary color lights are within the standard color coordinate ranges of the plurality of primary color lights; when the test color coordinates of one or more primary color lights are not within the standard color coordinate ranges of the corresponding primary color lights, determining target color coordinates and target white balance color temperatures of a plurality of primary color lights, and adjusting the test color coordinates of one or more primary color lights to be within standard color coordinate ranges of the corresponding primary color lights.
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公开(公告)号：US12147137B2
公开(公告)日：2024-11-19
申请号：US18380203
申请日：2023-10-16
Inventor： Maoxiu Zhou , Yanping Liao , Yingmeng Miao , Yuntian Zhang , Lei Guo , Ke Dai , Haipeng Yang , Zhihua Sun , Xibin Shao , Zhangtao Wang
IPC: G02F1/1362 , G02F1/1368
Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.
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Patent Agency Ranking
公开(公告)号：US12107089B2
公开(公告)日：2024-10-01
申请号：US17294968
申请日：2020-09-02
Inventor： Xibin Shao , Yanping Liao , Huibin Guo
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1225 , H01L29/7869
Abstract: An oxide thin film transistor includes a gate electrode, and a first active layer structure and a second active layer structure arranged subsequently, the first active layer structure includes a first conductive connection portion and a second conductive connection portion arranged oppositely, the second active layer structure includes a third conductive connection portion and a fourth conductive connection portion arranged oppositely, and the second oxide semiconductor pattern respectively coupled to the third conductive connection portion and the fourth conductive connection portion, and an orthographic projection of the first oxide semiconductor pattern on the substrate and an orthographic projection of the second oxide semiconductor pattern on the substrate are both located within an orthographic projection of the gate electrode on the substrate, the second conductive connection portion is coupled to the third conductive connection portion.
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公开(公告)号：US12107073B2
公开(公告)日：2024-10-01
申请号：US17429929
申请日：2020-10-27
Inventor： Zhihua Sun , Yanping Liao , Seungmin Lee , Qiujie Su , Feng Qu , Yingmeng Miao , Xibin Shao
IPC: H01L25/065 , H01L25/00 , H01L23/12
CPC classification number: H01L25/0655 , H01L25/50 , H01L23/12
Abstract: A display device and a method for bonding the display device are provided. The display device includes a display panel and a plurality of chip on films. The plurality of chip on films are arranged along a first edge of the display panel, and are divided into a plurality of groups of chip on films, and each group of chip on films includes at least two chip on films, and is bonded to the display panel through a same anisotropic conductive film.
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公开(公告)号：US12039907B2
公开(公告)日：2024-07-16
申请号：US18457637
申请日：2023-08-29
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2310/08
Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1≤k≤K≤N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n−i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1
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公开(公告)号：US12032237B2
公开(公告)日：2024-07-09
申请号：US18211008
申请日：2023-06-16
Inventor： Xibin Shao , Xiaona Liu , Rui Zhang
IPC: G02F1/1335 , G02F1/1339 , G02F1/1343
CPC classification number: G02F1/133514 , G02F1/1339 , G02F1/134336
Abstract: A display panel and a display apparatus. The display panel includes an array substrate and a color filter substrate opposite to each other, the array substrate being provided with a plurality of pixel regions arranged in an array, and the pixel regions closest to corners of the array substrate being first-type pixel regions, where the color filter substrate includes: a base substrate; a sealant between the base substrate and the array substrate; and a color filter layer on the base substrate and including a plurality of filter units, where the filter units includes first filter units corresponding to the first-type pixel regions, a portion of an orthographic projection of the first filter unit onto the base substrate facing a corner of the base substrate has a non-right-angle contour, and orthographic projections of the first filter unit and the sealant onto the base substrate do not overlap with each other.
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公开(公告)号：US11829041B2
公开(公告)日：2023-11-28
申请号：US17312427
申请日：2020-09-07
Inventor： Maoxiu Zhou , Yanping Liao , Yingmeng Miao , Yuntian Zhang , Lei Guo , Ke Dai , Haipeng Yang , Zhihua Sun , Xibin Shao , Zhangtao Wang
IPC: G02F1/1362 , G02F1/1368
CPC classification number: G02F1/136286 , G02F1/1368 , G02F1/136227
Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.
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