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    System power management using communication bus protocols
    51.
    发明授权
    System power management using communication bus protocols 有权

    公开(公告)号：US11181971B2

    公开(公告)日：2021-11-23

    申请号：US16780817

    申请日：2020-02-03

    Applicant: Apple Inc.

    Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

    IPC: G06F1/3296 ,  G06F1/06 ,  G06F1/3206 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/08 ,  G06F1/3237

    Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

    Software fault monitoring
    52.
    发明授权
    Software fault monitoring 有权

    公开(公告)号：US10915402B2

    公开(公告)日：2021-02-09

    申请号：US16129726

    申请日：2018-09-12

    Applicant: Apple Inc.

    Inventor： Zhimin Chen ,  Timothy R. Paaske ,  Yannick L. Sierra ,  Anish C. Trivedi

    IPC: G06F11/00 ,  G06F11/14 ,  G06F11/34 ,  G06F11/30

    Abstract: A method for verifying program flow during execution of a software program in a computer system is disclosed. Program code of the software program includes multiple program instructions and checkpoint data structures, where a given checkpoint data structure is associated with a given program instruction and is linked to at least one other checkpoint data structure. A fault monitor circuit may receive a particular checkpoint data structure and compare the particular checkpoint data structure to a previously received checkpoint data structure that is associated with another program instruction. Based on results of the comparison, the software fault monitor circuit may signal a program flow error.

    Control of a computer system in a power-down state
    53.
    发明授权
    Control of a computer system in a power-down state 有权

    公开(公告)号：US10747295B1

    公开(公告)日：2020-08-18

    申请号：US15721411

    申请日：2017-09-29

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Josh P. de Cesare

    IPC: G06F1/3287 ,  G06F1/26 ,  G06F9/4401 ,  G06F3/06 ,  G06F11/20

    Abstract: Techniques are disclosed relating a computer system in a power-down state receiving a communication from a remote computer system and performing a task indicated by the communication. The computer system in a power-down state performs the task without transitioning from the power-down state into a power-up state. Exemplary tasks performed in the power-down state include uploading one or more files to a remote computer system, downloading one or more files from a remote computer system, deleting one or more files from the computer system, accessing input/output devices, disabling the computer system, and performing a memory check on the computer system.

    Authentication and control of encryption keys
    54.
    发明授权
    Authentication and control of encryption keys 有权

    公开(公告)号：US10713351B2

    公开(公告)日：2020-07-14

    申请号：US16133625

    申请日：2018-09-17

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Weihua Mao ,  Shu-Yi Yu

    IPC: G06F21/00 ,  G06F21/46 ,  G06F21/60 ,  G06F21/44 ,  G06F21/85 ,  H04L9/08

    Abstract: An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.

    Silicon key attestation
    55.
    发明授权
    Silicon key attestation 有权

    公开(公告)号：US10536271B1

    公开(公告)日：2020-01-14

    申请号：US15435229

    申请日：2017-02-16

    Applicant: Apple Inc.

    Inventor： Thomas P. Mensch ,  Conrad Sauerwald ,  Jerrold V. Hauck ,  Timothy R. Paaske ,  Zhimin Chen ,  Andrew R. Whalley

    IPC: H04L9/08 ,  H04L9/14 ,  H04L9/30 ,  H04L9/32 ,  G06F21/70 ,  G06F21/73 ,  G06F21/57

    Abstract: Systems and methods are disclosed for generating one or more hardware reference keys (HRK) on a computing device, and for attesting to the validity of the hardware reference keys. An initial hardware reference key can be a silicon attestation key (SIK) generated during manufacture of a computing system, such as a system-on-a-chip. The SIK can comprise an asymmetric key pair based at least in part on an identifier of the processing system type and a unique identifier of the processing system. The SIK can be signed by the computing system and stored thereon. The SIK can be used to generate further HRKs on the computing device that can attest to the processing system type of the computing device and an operating system version that was running when the HRK was generated. The computing device can generate an HRK attestation (HRKA) for each HRK generated on the computing system.

    Multi-cycle delay for communication buses
    60.
    发明授权
    Multi-cycle delay for communication buses 有权
    通讯总线多循环延时

    公开(公告)号：US09262362B2

    公开(公告)日：2016-02-16

    申请号：US14041818

    申请日：2013-09-30

    Applicant: Apple Inc.

    Inventor： Shu-Yi Yu ,  Timothy R. Paaske

    IPC: G06F3/00 ,  G06F5/00 ,  G06F13/40 ,  G06F9/38

    CPC classification number: G06F13/4068 ,  G06F9/3869 ,  G06F13/4217 ,  G06F2213/0038

    Abstract: A system is disclosed that may compensate for bus timing that may vary over operating conditions of a bus. The system may include a communication bus, a first functional unit configured to transmit data via the communication bus, and a second functional unit configured to receive data via the bus. The first functional unit may transmit a first value via the communication bus to the second functional unit. The first functional unit may be further configured to assert a data valid signal responsive to a determination that a first time period has elapsed since the transmission of the first data value. The second functional unit may be configured to receive the first data value and sample the first data value dependent upon the data valid signal.

    Abstract translation: 公开了可以补偿可能随总线的操作条件而变化的总线时序的系统。 该系统可以包括通信总线，被配置为经由通信总线发送数据的第一功能单元和被配置为经由总线接收数据的第二功能单元。 第一功能单元可以经由通信总线向第二功能单元发送第一值。 第一功能单元还可以被配置为响应于从发送第一数据值开始经过第一时间段的确定来断言数据有效信号。 第二功能单元可以被配置为接收第一数据值并且取决于数据有效信号对第一数据值进行采样。

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