公开(公告)号：US09837048B2

公开(公告)日：2017-12-05

申请号：US14682321

申请日：2015-04-09

Applicant: ARM Limited

Inventor： Daren Croxford ,  Sean Tristram Ellis

IPC: G09G5/10 ,  G09G3/34 ,  G09G5/393

CPC classification number: G09G5/10 ,  G09G3/34 ,  G09G5/393 ,  G09G2320/0626 ,  G09G2340/02 ,  G09G2350/00 ,  G09G2360/144 ,  G09G2360/16

Abstract: A data processing system 30 includes a CPU 33, a GPU 34, a video processing engine (video engine) 35, a display controller 36 (or an image processing engine) and a memory controller 313 all having access to off-chip memory 314. A frame to be displayed is generated by, for example, being appropriately rendered by the GPU 34 or video engine 35. The display controller 36 (or the image processing engine) then performs display modifications, such as luminance compensation, on the frame to provide an output frame for display.The display controller 36 (or the image processing engine) also provides display modification information (such as determined luminance compensation parameters) to the GPU 33 and video engine 34. The display modification information is then used to modify the data that is generated for a frame to be displayed.

公开(公告)号：US09678889B2

公开(公告)日：2017-06-13

申请号：US14579483

申请日：2014-12-22

Applicant: ARM Limited

Inventor： Roko Grubisic ,  Andrew Burdass ,  Daren Croxford ,  Isidoros Sideris

IPC: G06F12/00 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/304 ,  Y02D10/13

Abstract: Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.

公开(公告)号：US09472008B2

公开(公告)日：2016-10-18

申请号：US14309487

申请日：2014-06-19

Applicant: ARM Limited

Inventor： Daren Croxford ,  Thomas James Cooksey ,  Sean Tristram Ellis

IPC: G06T11/60 ,  G06T11/40 ,  G06T15/00

CPC classification number: G06T11/60 ,  G06T11/40 ,  G06T15/005

Abstract: A graphics processing apparatus performs tile based compositing operations. Tile metadata includes flag data, such as transparency and/or intensity flag data, indicating whether a given input graphics tile makes less than a predetermined first threshold level of contribution or more than a second predetermined threshold level of contribution to a corresponding output graphics tile. For example, if an input graphics tile is transparent, then its reading from a memory and/or subsequent processing may be suppressed. If a given input graphics tile is opaque, then underlying input graphics tiles that are obscured may have their reading and/or further processing suppressed.

Abstract translation: 图形处理装置执行基于瓦片的合成操作。 平铺元数据包括诸如透明度和/或强度标志数据的标志数据，其指示给定的输入图形图块是否小于预定的第一阈值贡献水平，或者大于对相应输出图形图块的第二预定阈值水平。 例如，如果输入图形瓦片是透明的，则可以抑制其从存储器读取和/或后续处理。 如果给定的输入图形瓦片是不透明的，则隐藏的底层输入图形瓦片可以抑制其读取和/或进一步的处理。

公开(公告)号：US20150356953A1

公开(公告)日：2015-12-10

申请号：US14727016

申请日：2015-06-01

Applicant: ARM Limited

Inventor： Damian Modrzyk ,  Pawel Duc ,  Piotr Chrobak ,  Michal Bogusz ,  Daren Croxford

IPC: G09G5/36 ,  G09G5/00 ,  G09G5/12 ,  G09G5/14 ,  G09G5/393

CPC classification number: G09G5/363 ,  G09G5/003 ,  G09G5/006 ,  G09G5/12 ,  G09G5/14 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/02 ,  G09G2340/0407 ,  G09G2340/0492 ,  G09G2340/12 ,  G09G2360/02 ,  G09G2360/06 ,  G09G2360/128 ,  G09G2360/18

Abstract: A display controller comprises an input stage 20 operable to read at least one input surface, a composition stage 28 operable to compose plural input surfaces to generate a composited output surface, an output stage 30 operable to provide the composited output surface to a display for display, a scaling engine 31 operable to scale a composited output surface generated by the composition stage 28, and a write-out stage 32 operable to write a composited and/or scaled output surface to external memory.

Abstract translation: 显示控制器包括可操作以读取至少一个输入表面的输入级20，可操作以组合多个输入表面以生成合成输出表面的合成台28，可操作以将合成输出表面提供给显示器进行显示的输出级30 缩放引擎31，其可操作以缩放由构图阶段28生成的合成输出表面;以及写出阶段32，其可操作以将合成和/或缩放的输出表面写入外部存储器。

公开(公告)号：US11995532B2

公开(公告)日：2024-05-28

申请号：US16210389

申请日：2018-12-05

Applicant: Arm Limited

Inventor： Daren Croxford

IPC: G06N3/063 ,  G06N3/08 ,  G06N20/10

CPC classification number: G06N3/063 ,  G06N3/08 ,  G06N20/10

Abstract: Subject matter disclosed herein may relate to storage and/or processing of signals and/or states representative of neural network parameters in a computing device, and may relate more particularly to configuring circuitry in a computing device to process signals and/or states representative of neural network parameters.

公开(公告)号：US11995475B2

公开(公告)日：2024-05-28

申请号：US17082864

申请日：2020-10-28

Applicant: Apical Limited ,  Arm Limited

Inventor： Daren Croxford ,  Sharjeel Saeed ,  Jayavarapu Srinivasa Rao ,  Aaron Debattista

IPC: G06F9/50 ,  G06F3/06 ,  G06N3/04

CPC classification number: G06F9/5038 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0673 ,  G06F9/505 ,  G06N3/04

Abstract: An information processing apparatus is described for processing a workload. The information processing apparatus comprises a processor and a memory element connected to the processor via a data link. In advance of processing a workload, the information processing apparatus estimates an access time required to transfer an amount of the workload that is to be transferred from the external memory element to the processor, and estimates a processing time for the processor to process the workload. A processing rate characteristic of the processor and/or a data transfer rate between the memory and the processor is set in dependence upon the estimated processing time and estimated access time. Methods for varying a quality of service (QoS) value of requests to the external memory element are also described.

公开(公告)号：US20240036932A1

公开(公告)日：2024-02-01

申请号：US18359002

申请日：2023-07-26

Applicant: Arm Limited

Inventor： Daren Croxford ,  Sharjeel Saeed ,  Isidoros Sideris

IPC: G06F9/50 ,  G06T15/00

CPC classification number: G06F9/505 ,  G06T15/005

Abstract: Disclosed herein is a graphics processor that comprises a programmable execution unit operable to execute programs to perform graphics processing operations. The graphics processor further comprises a dedicated machine learning processing circuit operable to perform processing operations for machine learning processing tasks. The machine learning processing circuit is in communication with the programmable execution unit internally to the graphics processor. In this way, the graphics processor can be configured such that machine learning processing tasks can be performed by the programmable execution unit, the machine learning processing circuit, or a combination of both, with the different units being able to message each other accordingly to control the processing.

公开(公告)号：US11874469B2

公开(公告)日：2024-01-16

申请号：US17649754

申请日：2022-02-02

Applicant: Arm Limited

Inventor： Daren Croxford ,  Roberto Lopez Mendez

IPC: G02B27/01 ,  G06F3/01

CPC classification number: G02B27/0172 ,  G06F3/013 ,  G02B2027/014 ,  G02B2027/0138 ,  G02B2027/0174 ,  G02B2027/0178

Abstract: A method of controlling an imaging system for a Head Mounted Display (HMD) device. The method comprises capturing an external scene, for example using a camera, determining an attenuation pattern, for rendering a filter area. The method also comprises determining, based on the captured external scene, a compensation pattern to for compensating at least part of the filter area, attenuating the external scene using the attenuation pattern and generating a holographic image of a virtual object, the holographic image including the compensation pattern.

公开(公告)号：US20230252264A1

公开(公告)日：2023-08-10

申请号：US17669301

申请日：2022-02-10

Applicant: Arm Limited

Inventor： Daren Croxford ,  Rachel Jean Trimble ,  Sharjeel Saeed ,  Roberto Lopez Mendez

IPC: G06N3/04 ,  G06V10/82

CPC classification number: G06N3/04 ,  G06V10/82

Abstract: When executing a neural network comprising a sequence of plural layers of neural network processing in which at least one of the layers of the sequence of plural layers of the neural network is followed by two or more branches of neural network processing, each branch comprising a different sequence of one or more layers of neural network processing, the branch or branches to use for the neural network processing following the layer of the neural network that is followed by the two or more branches of neural network processing is selected based on a property or properties of the output feature map from the layer that is followed by the two or more branches.

公开(公告)号：US11562715B2

公开(公告)日：2023-01-24

申请号：US17005964

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Daren Croxford ,  Guy Larri

IPC: G09G5/36 ,  G09G5/37 ,  A63F13/53 ,  G06T1/20

Abstract: When a graphics processor is processing data for an application on a host processor, the graphics processor generates in advance of their being required for display by the application a plurality of frame sequences corresponding to a plurality of different possible “future states” for the application. The graphics processing system, when producing a frame in a sequence of frames corresponding to a given future state for the application, determines one or more region(s) of the frame that are to be produced at a first, higher quality, and producing the determined region(s) of the frame at a first, higher quality, whereas other regions of the frame are produced at a second, lower quality.