公开(公告)号：US20250029775A1

公开(公告)日：2025-01-23

申请号：US18354945

申请日：2023-07-19

Applicant: STMICROELECTRONICS INTERNATIONAL N.V ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  UNIVERSITE DE BORDEAUX

Inventor： Sebastien SADLO ,  Nathalie DELTIMPLE ,  Andreia CATHELIN

IPC: H01F27/28 ,  H01F27/29 ,  H01F37/00

Abstract: An interleaved coupled inductors transformer is described in accordance with various embodiments of the present disclosure. In various embodiments, the interleaved coupled inductors transformer includes a first terminal including a first port, a first branch of the first terminal, and a second branch of the first terminal approximately parallel to with the first branch of the first terminal. The interleaved coupled inductors transformer includes a second terminal spatially separate from the first terminal, the second terminal including a second port, a first branch of the second terminal, a second branch of the second terminal approximately parallel to with the first branch of the second terminal, wherein the first and second branches of the first terminal do not overlap with the first and second branches of the second terminal.

公开(公告)号：US20250028944A1

公开(公告)日：2025-01-23

申请号：US18355767

申请日：2023-07-20

Applicant: STMicroelectronics International N.V.

Inventor： Jack Iain Maclean ,  Brian Douglas Stewart

IPC: G06N3/049 ,  H03H11/04 ,  H03K17/687

Abstract: According to an embodiment, a max-pooling neuron with first and second integrator circuits, a comparator circuit, a Schmitt trigger circuit, and a pair of switches is provided. The first and second integrator circuits, respectively filter a first and a second input train from a first and a second neuron of a previous layer to generate a corresponding first and second filtered input train. The comparator circuit amplifies a difference between the first and second filtered input trains and generates an amplified differential signal. The Schmitt trigger circuit generates a binary output signal based on the amplified differential signal. The pair of switches have a common first terminal coupled to an output node of the max-pooling neuron and a common control terminal coupled to the output terminal of the Schmitt trigger circuit. The other terminals of the pair of switches are coupled to respective input trains.

公开(公告)号：US20250027994A1

公开(公告)日：2025-01-23

申请号：US18222535

申请日：2023-07-17

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep JAIN ,  Shalini PATHAK ,  Pooja JAIN

IPC: G01R31/3185 ,  G01R31/317

Abstract: An integrated circuit improves scan testing efficiency by addressing slow Scan-OUT pins. The integrated circuit shifts data through high-frequency Scan-OUT pins every cycle and through low-frequency Scan-OUT pins every other cycle. Data that cannot be shifted through low-frequency pins is stored in an accumulator and later shifted out through high-frequency pins. Despite changing the scan-out data pattern, the tester used for testing the integrated circuit anticipates the resulting pattern, providing for the testing to not be negatively impacted.

公开(公告)号：US12203982B2

公开(公告)日：2025-01-21

申请号：US17663561

申请日：2022-05-16

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh Narwal ,  Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/30 ,  G01R31/317 ,  G01R31/3173 ,  G01R31/319

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

公开(公告)号：US20250023474A1

公开(公告)日：2025-01-16

申请号：US18763665

申请日：2024-07-03

Applicant: STMicroelectronics International N.V.

Inventor： Vratislav MICHAL

IPC: H02M3/158 ,  H05B47/10

Abstract: A power conversion circuit includes a first node configured to receive a first voltage referenced to a second node configured to be coupled to a reference potential. A first power converter couples the first node to a third node. A second power converter couples a fourth node to an output node. A first capacitor couples the third node to the fourth node. A first switch connects the output node to the first node. An output switch connects the output node to a load.

公开(公告)号：US20250022820A1

公开(公告)日：2025-01-16

申请号：US18349351

申请日：2023-07-10

Applicant: STMicroelectronics International N.V.

Inventor： Mohamed BOUFNICHEL

IPC: H01L23/00

Abstract: Methods, systems, and devices for semiconductor manufacturing are described. One such method includes forming a first layer comprising a first material. A top surface of the first layer extends along a first direction and a second direction. In some cases, the method includes forming, on at least the top surface of the first layer, a second layer comprising a second material, and forming a void in the second layer. Forming the void may expose a portion of the top surface of the first layer. In some cases, the method may include forming one or more layers on a top surface of the second layer and on the exposed portion of the top surface of the first layer. The method may also include performing a material removal operation that lifts portions of the one or more layers formed on the top surface of the second layer off of the top surface.

公开(公告)号：US20250015145A1

公开(公告)日：2025-01-09

申请号：US18348012

申请日：2023-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Simone RASCUNA' ,  Paolo BADALA' ,  Gabriele BELLOCCHI ,  Valeria PUGLISI

IPC: H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/872

Abstract: A method for forming an ohmic contact on a semiconductor component, for example a high-power electrical diode, is provided. An example method includes depositing a first metal layer on a top surface of a semiconductor drift layer having an electrical contact point, the first metal layer highly reflective of a laser light. The method further includes depositing a second metal layer on portions of the first metal layer aligned with the electrical contact point, the second metal layer selected to absorb the laser light. The method further includes exposing the first and the second metal layers to the laser light in a laser annealing process, causing the second metal layer to substantially increase in temperature due to the laser light. The increase in temperature of the second metal layer causing the ohmic contact to form between the electrical contact point and the first metal layer.

公开(公告)号：US20250015038A1

公开(公告)日：2025-01-09

申请号：US18757887

申请日：2024-06-28

Applicant: STMicroelectronics International N.V.

Inventor： Pierangelo MAGNI ,  Alberto ARRIGONI ,  Giovanni MISSAGLIA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor die is mounted on a substrate having electrically conductive substrate portions. The electrically conductive substrate portions include a die mounting location and electrically conductive leads around the die mounting location. The semiconductor die is mounted on a first surface of the die mounting location. The substrate and the semiconductor die are encapsulated in an electrically insulating encapsulation having a surface opposite the first surface. An electrically conductive path is provided to electrically couple the semiconductor die to one of the electrically conductive substrate portions. The electrically conductive path includes: a first path section extending through and/or over the electrically insulating encapsulation between the electrically conductive substrate portion and an intermediate point at the surface of the electrically insulating encapsulation, and a second path section provided via wire bonding and extending between the semiconductor die and the intermediate point at the surface of the electrically insulating encapsulation.

公开(公告)号：US20250013739A1

公开(公告)日：2025-01-09

申请号：US18737583

申请日：2024-06-07

Applicant: STMicroelectronics International N.V.

Inventor： Luca Di Cosmo

IPC: G06F21/53 ,  G06F21/54 ,  G06F21/60

Abstract: Described is a method for performing the execution of an application in a Secure Element (SE), comprising a host sending an APDU command to the SE comprising the application, processing at the SE the APDU command for execution by the application, performing a determined plurality of operations of the application commanded by the APDU command, the application determining among the plurality of application operations commanded by the APDU command a first set of operations to be executed by the application upon receiving the APDU command and at least a second set of operations. The SE performs the first set of operations to be executed by the application upon receiving the APDU command, performing a deferred execution of a second set of operations upon communication of completion of the execution of the first set of operations from the SE to the host.

公开(公告)号：US20250013257A1

公开(公告)日：2025-01-09

申请号：US18750152

申请日：2024-06-21

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Atul DWIVEDI

IPC: G05F3/30 ,  G01K7/01 ,  G01K7/16

Abstract: An integrated circuit comprises a current source, a plurality of transistors arranged in parallel, a plurality of resistors, a plurality of switches, switch control circuitry, and measurement circuitry. Each resistor is coupled with the emitter of a respective transistor. Each switch selectively couples the current source to a respective resistor such that a bias current flows from the current source to the emitter of a respective transistor when a respective switch is closed. The measurement circuitry is coupled to the first transistor between its emitter and a respective resistor. The measurement circuitry is configured to separately measure a base-emitter voltage (VBE1) of the first transistor when all of the switches are closed and a base-emitter voltage (VBE2) of the first transistor when only the switch associated with the first transistor is closed and to determine a ΔVBE by calculating a difference between VBE2 and VBE 1.