公开(公告)号：US08334551B2

公开(公告)日：2012-12-18

申请号：US13120987

申请日：2009-08-25

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

摘要翻译： 每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。 对于每个存储块，存储器串按第二方向布置有m列。 布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。 满足式（1）所示的关系：（式1）m> = n

公开(公告)号：US08330216B2

公开(公告)日：2012-12-11

申请号：US12345088

申请日：2008-12-29

申请人： Yosuke Komori ,  Masaru Kito ,  Megumi Ishiduki ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Yosuke Komori ,  Masaru Kito ,  Megumi Ishiduki ,  Ryota Katsumata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/66

CPC分类号： H01L29/792 ,  H01L21/8221 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/7926

摘要： A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.

摘要翻译： 非挥发性半导体存储器件包括第一柱状半导体层和形成为使得用于存储电荷的电荷存储层夹在第一导电层和第一柱状半导体层之间的多个第一导电层。 此外，非挥发性半导体存储器件包括第二柱状半导体层和形成为使得绝缘层夹在第二导电层和第二柱状半导体层之间的第二导电层，第二导电层重复地设置在一行中 通过在与层叠方向垂直的第一方向上设置一定间隔来形成。 沿着第二导电层的纵向方向在侧壁上形成与第二导电层接触并沿第一方向延伸的第一侧壁导电层。

公开(公告)号：US20120241844A1

公开(公告)日：2012-09-27

申请号：US13236833

申请日：2011-09-20

申请人： Tadashi IGUCHI ,  Ryota KATSUMATA

发明人： Tadashi IGUCHI ,  Ryota KATSUMATA

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L23/481 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40117 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: first and second stacked bodies, first and second semiconductor pillars, a connection portion, a memory film, and a partitioning insulating layer. The stacked bodes include electrode films stacked along a first axis and an inter-electrode insulating film provided between the electrode films. Through-holes are provided in the stacked bodies. The semiconductor pillars are filled into the through-holes. The connection portion electrically connects the semiconductor pillars. The memory film is provided between the semiconductor pillars and the electrode films. The partitioning insulating layer partitions the first and second electrode films. A side surface of the first through-hole on the partitioning insulating layer side and a side surface of the second through-hole on the partitioning insulating layer side have a portion parallel to a plane orthogonal to a second axis from the first stacked body to the second stacked body.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：第一和第二堆叠体，第一和第二半导体柱，连接部分，存储膜和分隔绝缘层。 堆叠的栅极包括沿着第一轴线堆叠的电极膜和设置在电极膜之间的电极间绝缘膜。 在堆叠体中设置有通孔。 半导体柱被填充到通孔中。 连接部电连接半导体支柱。 存储膜设置在半导体柱和电极膜之间。 分隔绝缘层分隔第一和第二电极膜。 分隔绝缘层侧的第一通孔的侧面和分隔绝缘层侧的第二贯通孔的侧面具有与从第一层叠体到第二贯通孔的第二轴正交的平面的部分 第二堆叠体。

公开(公告)号：US08274108B2

公开(公告)日：2012-09-25

申请号：US12705231

申请日：2010-02-12

申请人： Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/0688 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, the electrode films being divided to form a plurality of control gate electrodes aligned in a first direction; a plurality of semiconductor pillars aligned in a stacking direction of the stacked body, the semiconductor pillars being arranged in a matrix configuration along the first direction and a second direction intersecting the first direction to pierce the control gate electrodes; and a connection member connecting a lower end portion of one of the semiconductor pillars to a lower end portion of one other of the semiconductor pillars, an upper end portion of the one of the semiconductor pillars being connected to a source line, an upper end portion of the one other of the semiconductor pillars being connected to a bit line. At least some of the control gate electrodes are pierced by two of the semiconductor pillars adjacent to each other in the second direction. Two of the semiconductor pillars being connected to each other by the connection member pierce mutually different control gate electrodes.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠体，包括交替层叠有多个电极膜的多个绝缘膜，所述电极膜被分割以形成沿第一方向排列的多个控制栅电极; 多个半导体柱沿堆叠体的堆叠方向排列，半导体柱沿着第一方向以矩阵构造排列，第二方向与第一方向相交以刺穿控制栅电极; 以及将所述半导体柱之一的下端部连接到所述半导体柱的另一个的下端部的连接部件，所述一个半导体柱的上端部与源极线连接，上端部 另一个半导体柱被连接到位线。 至少一些控制栅极电极在第二方向上被彼此相邻的两个半导体柱刺穿。 通过连接构件彼此连接的两个半导体柱穿透彼此不同的控制栅电极。

公开(公告)号：US08253187B2

公开(公告)日：2012-08-28

申请号：US12142289

申请日：2008-06-19

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kido ,  Hideaki Aochi ,  Mitsuru Sato ,  Yasuyuki Matsuoka

IPC分类号： H01L27/115

CPC分类号： H01L27/115 ,  H01L27/11556

摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.

摘要翻译： 非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。 存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管 。 漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于 漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

公开(公告)号：US20110316069A1

公开(公告)日：2011-12-29

申请号：US12886010

申请日：2010-09-20

申请人： Hiroyasu TANAKA ,  Ryota KATSUMATA

发明人： Hiroyasu TANAKA ,  Ryota KATSUMATA

IPC分类号： H01L29/792

CPC分类号： H01L27/11551 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a non-memory unit. The memory unit includes a stacked structure including electrode films stacked in a first direction, and a interelectrode insulating film provided between the electrode films, a select gate electrode stacked with the stacked structure along the first direction, a semiconductor pillar piercing the stacked structure and the select gate electrode along the first direction and a pillar portion memory layer provided between the electrode films and the semiconductor pillar. The non-memory unit includes a dummy conductive film including a portion in a layer being identical to at least one of the electrode films, a dummy select gate electrode in a layer being identical to the select gate electrode, a first non-memory unit contact electrode electrically connected to the dummy conductive and a second non-memory unit contact electrode electrically connected to the dummy select gate.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储器单元和非存储器单元。 存储单元包括堆叠结构，其包括在第一方向上堆叠的电极膜，以及设置在电极膜之间的电极间绝缘膜，沿着第一方向堆叠层叠结构的选择栅电极，穿过层叠结构的半导体柱和 沿着第一方向选择栅电极和设置在电极膜和半导体柱之间的柱部存储层。 非存储单元包括虚拟导电膜，其包括与至少一个电极膜相同的层中的部分，与选择栅电极相同的层中的虚拟选择栅电极，第一非存储单元触点 电连接到虚拟导电体的电极和与虚拟选择栅极电连接的第二非存储单元接触电极。

公开(公告)号：US08084807B2

公开(公告)日：2011-12-27

申请号：US12535847

申请日：2009-08-05

申请人： Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.

摘要翻译： 通过在与硅衬底的上表面正交的方向上交替堆叠用作控制栅极和电介质膜的电极膜来形成多层体。 在多层体中形成在字线方向上延伸的沟槽，并且在沟槽的内表面上形成记忆膜。 随后，将硅体埋在沟槽内，并且电荷存储膜和硅体在字线方向上分开以形成硅柱。 这简化了位线方向上的存储单元的配置，因此可以缩短硅柱的排列间距，减小每个存储单元的面积。

公开(公告)号：US20110284947A1

公开(公告)日：2011-11-24

申请号：US13198359

申请日：2011-08-04

申请人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru KITO ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US08017993B2

公开(公告)日：2011-09-13

申请号：US12405522

申请日：2009-03-17

申请人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/42348

摘要： A nonvolatile semiconductor memory device includes: a stacked body with a plurality of insulating films and electrode films alternately stacked therein, through which a through hole extending in the stacking direction is formed; a semiconductor pillar buried inside the through hole; and a charge storage layer located on both sides of each of the electrode films in the stacking direction and insulated from the electrode film and the semiconductor pillar.

摘要翻译： 非易失性半导体存储器件包括：具有交替堆叠的多个绝缘膜和电极膜的堆叠体，通过该堆叠体形成沿层叠方向延伸的通孔; 埋在通孔内的半导体柱; 以及电荷存储层，其位于层叠方向上的每个电极膜的两侧，并与电极膜和半导体柱绝缘。

公开(公告)号：US07982261B2

公开(公告)日：2011-07-19

申请号：US12563832

申请日：2009-09-21

申请人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

发明人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion.

摘要翻译： 非易失性半导体存储器件包括在硅衬底上的第一层叠体，并且在其上设置第二层叠体。 第一堆叠体包括交替层叠有多个电极膜的多个绝缘膜，并且形成沿堆叠方向延伸的通孔的第一部分。 第二堆叠体包括交替层叠有多个电极膜的多个绝缘膜，并且形成通孔的第二部分。 在通孔的内表面上形成记忆膜，并且将硅柱埋在通孔的内部。 通孔的第二部分的中心轴线从第一部分的中心轴线偏移，并且第二部分的下端位于比第一部分的上部更低的位置。