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    BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES
    51.
    发明申请
    BIAS-CONTROLLED DEEP TRENCH SUBSTRATE NOISE ISOLATION INTEGRATED CIRCUIT DEVICE STRUCTURES 有权
    偏置控制深度底板噪声隔离集成电路设备结构

    公开(公告)号：US20110018094A1

    公开(公告)日：2011-01-27

    申请号：US12506270

    申请日：2009-07-21

    申请人： Phillip Francis Chapman ,  David Goren ,  Rajendran Krishnasamy ,  Benny Sheinman ,  Shlomo Shlafman ,  Raminderpal Singh ,  Wayne H. Woods

    发明人： Phillip Francis Chapman ,  David Goren ,  Rajendran Krishnasamy ,  Benny Sheinman ,  Shlomo Shlafman ,  Raminderpal Singh ,  Wayne H. Woods

    IPC分类号： H01L29/92 ,  H01L21/02 ,  G06F17/50

    CPC分类号： H01L29/945 ,  H01L29/66181

    摘要： A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques

    摘要翻译： 一种用于在半导体芯片上的集成电路器件之间提供噪声隔离的新型有用的装置和方法。 本发明解决了由集成电路芯片中的数字开关器件产生的噪声的问题，该芯片可以通过硅衬底耦合到敏感的模拟电路（例如，PLL，收发器，ADC等）中，导致敏感模拟器的性能显着降低 电路。 本发明利用连接到地的深沟槽电容器（DTCAP）器件将受害电路与同一集成电路芯片上的侵扰器噪声源隔离开来。 与其他现有技术的屏蔽技术相比，电容器的深度穿透产生了深深的衬底中的接地屏蔽

    Single frequency low power RFID device
    53.
    发明授权
    Single frequency low power RFID device 有权
    单频低功率RFID设备

    公开(公告)号：US07576657B2

    公开(公告)日：2009-08-18

    申请号：US11529733

    申请日：2006-09-29

    申请人： Mark Duron ,  James Giebel ,  David Goren ,  Thomas Wulff ,  Richard T. Knadle, Jr. ,  Christopher Brock

    发明人： Mark Duron ,  James Giebel ,  David Goren ,  Thomas Wulff ,  Richard T. Knadle, Jr. ,  Christopher Brock

    IPC分类号： G08B13/14

    CPC分类号： G06K7/0008

    摘要： Methods, systems, and apparatuses for a reader transceiver circuit are described. The reader transceiver circuit incorporates a frequency generator, such as a surface acoustic wave (SAW) oscillator. A reader incorporating the reader transceiver circuit is configured to read a tag at very close range, including while being in contact with the tag. The transceiver can be coupled to various host devices in a variety of ways, including being located in a RFID reader (e.g., mobile or fixed position), a computing device, a barcode reader, etc. The transceiver can be located in an RFID module that is attachable to a host device, can be configured in the host device, or can be configured to communicate with the host device over a distance. The RFID module may include one or more antennas, such as a first antenna configured to receive a magnetic field component of an electromagnetic wave and a second antenna configured to receive an electric field component of an electromagnetic wave. The RFID module may include a detector that is configured to determine if the RFID module is positioned in proximity to an object, such as a RFID tag. The detector may operate as a trigger for the RFID module, to enable or trigger a function of the RFID module.

    摘要翻译： 描述了用于读取器收发器电路的方法，系统和装置。 读取器收发器电路包括频率发生器，例如表面声波（SAW）振荡器。 包括读取器收发器电路的读取器被配置为在非常接近的范围内读取标签，包括在与标签接触的同时。 收发器可以以各种方式耦合到各种主机设备，包括位于RFID读取器（例如，移动或固定位置），计算设备，条形码读取器等中。收发器可以位于RFID模块中 可附接到主机设备，可以在主机设备中配置，或者可以被配置为在一定距离上与主机设备进行通信。 RFID模块可以包括一个或多个天线，诸如被配置为接收电磁波的磁场分量的第一天线和被配置为接收电磁波的电场分量的第二天线。 RFID模块可以包括被配置为确定RFID模块是否位于诸如RFID标签之类的物体附近的检测器。 检测器可以用作RFID​​模块的触发器，以实现或触发RFID模块的功能。

    Method and system for calculating high frequency limit capacitance and inductance for coplanar on-chip structure
    56.
    发明授权
    Method and system for calculating high frequency limit capacitance and inductance for coplanar on-chip structure 失效
    用于计算共面片上结构的高频限制电容和电感的方法和系统

    公开(公告)号：US07434186B1

    公开(公告)日：2008-10-07

    申请号：US11948761

    申请日：2007-11-30

    申请人： David Goren ,  Benny Sheinman ,  Shlomo Shlafman

    发明人： David Goren ,  Benny Sheinman ,  Shlomo Shlafman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Capacitance and inductance expressions used for modeling critical on-chip metal interconnects. A method for calculating high frequency limit capacitances C∞ and inductances L∞ of coplanar transmission line structures over silicon substrate utilizes field based expressions derived for a single coplanar T-line structures over silicon, and coupled coplanar T lines over silicon. For coupled coplanar structures, the field lines based calculation is performed separately for odd and even modes.

    摘要翻译： 用于建模关键片上金属互连的电容和电感表达式。 用于计算硅衬底上的共面传输线结构的高频限制电容C∞和电感L∞的方法利用基于单个共面T线结构导出的基于场的表达式 硅和耦合的共面T线在硅上。 对于耦合共面结构，对于奇数和偶数模式分别执行基于场线的计算。

    CAPACITANCE MODELING
    57.
    发明申请
    CAPACITANCE MODELING 有权
    电容建模

    公开(公告)号：US20080244485A1

    公开(公告)日：2008-10-02

    申请号：US12137277

    申请日：2008-06-11

    申请人： Rachel Gordin ,  David Goren

    发明人： Rachel Gordin ,  David Goren

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method of modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-clip coplanar transmission lines over a conductive substrate operated at very high frequencies, such that the substrate behaves as a perfect dielectric. It is assumed that the surrounding dielectric material is a first dielectric with a first permittivity (∈1) and the substrate is a second dielectric with a second permittivity (∈2). The method models the capacitance (C1) for values of the first and second permittivity (∈1, ∈2) based on known capacitance (C2) computed for a basis structure with the same first permittivity (∈1) and a different second permittivity (∈2). Extrapolation or interpolation formulae are suggested to model the sought capacitance (C1) through one or more known capacitances (C2).

    摘要翻译： 一种用于结构建模的方法，该结构包括由电介质材料包围并由衬底支撑的一对长导体。 特别地，该结构可以是在以非常高的频率操作的导电衬底上的夹具共面传输线，使得衬底表现为完美的电介质。 假设周围的电介质材料是具有第一介电常数（εε1）的第一电介质，并且衬底是具有第二介电常数（ε2 2 N 2）的第二电介质。 该方法基于已知的电容（第一和第二介电常数（∈1 SUB，∈2））的值来模拟电容（C 1> 对于具有相同的第一介电常数（εε1 1）的基础结构和不同的第二介电常数（ε2 2 N）计算出的数学公式（C 2＆lt; 2＆gt; 2）。 建议外推或内插公式，以通过一个或多个已知电容（C 2> 2）来建模所寻找的电容（C 1> 1）。

    Amplitude-offset invariant template detection for pulse position estimation; methods, systems and program products
    58.
    发明授权
    Amplitude-offset invariant template detection for pulse position estimation; methods, systems and program products 失效
    用于脉冲位置估计的幅度偏移不变模板检测; 方法，系统和程序产品

    公开(公告)号：US07197092B2

    公开(公告)日：2007-03-27

    申请号：US10242363

    申请日：2002-09-13

    申请人： David Hernandez ,  David Goren

    发明人： David Hernandez ,  David Goren

    IPC分类号： H03D1/00

    CPC分类号： H04B1/7075 ,  H04L25/03006

    摘要： A method and system of determining and correcting modulation and offset effects in a received signal. A signal [s(n)] is received subject to modulation effects A on pulse shape or peak [p(n)] and vertical offset B due to multipath where “n” is a pulse rate or samples of the signal. A template of length N incorporates a replica of the original signal [s(n)] without multipath or vertical offset. The template is normalized and generates either an extended template or a balanced template. The extended template is correlated with the received signal [s(n)] by shifting the extended template along the received signal to estimate modulation effects of A at a particular time, n. The average difference between the template and the modulated signal [p(n)] is calculated to determine the magnitude of the offset B for a particular time, n.

    摘要翻译： 一种确定和校正接收信号中的调制和偏移效应的方法和系统。 在脉冲形状或峰值[p（n）]上受到调制效应A的信号[s（n）]和由于多路径而产生的垂直偏移B，其中“n”是脉冲频率或信号样本。 长度为N的模板包含原始信号[s（n）]的复本，而不具有多径或垂直偏移。 模板被归一化，并生成扩展模板或平衡模板。 扩展模板与接收信号[s（n）]相关，通过沿着接收信号移位扩展模板来估计A在特定时间n的调制效应。 计算模板和调制信号[p（n）]之间的平均差异，以确定特定时间n的偏移量B的大小。

    Capacitance modeling
    59.
    发明申请
    Capacitance modeling 有权
    电容建模

    公开(公告)号：US20060286691A1

    公开(公告)日：2006-12-21

    申请号：US11153047

    申请日：2005-06-15

    申请人： David Goren ,  Shlomo Shlafman

    发明人： David Goren ,  Shlomo Shlafman

    IPC分类号： H01L21/66

    CPC分类号： G06F17/5036

    摘要： A method of modeling capacitance for all practical 2D on-chip wire structures including coplanar and microstrip structures. The method includes using a field lines approach (600) to obtain capacitance expressions for structure components, combining the expressions (704) for components of the subject structure and obtaining a capacitance expression (705) for the subject structure. The static capacitance matrix for the structure is calculated from the capacitance expression. The structure components can include components with parallel plate field lines, quarter circle field lines, singularity field lines, singularity field lines with restriction, double set of quarter circle field lines which are used as building blocks for the subject structure. The final capacitance expressions can be used for the modeling of critical on-chip wires and devices as well as inside a capacitance extraction tool.

    摘要翻译： 对于所有实际的2D片上线结构（包括共面和微带结构）的电容建模方法。 该方法包括使用场线方法（600）来获得结构分量的电容表达式，组合用于主题结构的分量的表达式（704）并获得用于该对象结构的电容表达式（705）。 根据电容表达式计算结构的静态电容矩阵。 结构部件可以包括具有平行板场线，四分之一圆场线，奇异场线，具有限制的奇异场线，具有双组四分之一圆场线的组件，它们被用作被摄体结构的构件。 最终的电容表达式可用于关键片上导线和器件以及电容提取工具中的建模。

    Device and method for reducing dishing of critical on-chip interconnect lines
    60.
    发明申请
    Device and method for reducing dishing of critical on-chip interconnect lines 审中-公开
    减少关键片上互连线的凹陷的装置和方法

    公开(公告)号：US20060072257A1

    公开(公告)日：2006-04-06

    申请号：US10954672

    申请日：2004-09-30

    申请人： Rachel Gordin ,  David Goren ,  Sue Strang ,  Kurt Tallman ,  Youri Tretiakov

    发明人： Rachel Gordin ,  David Goren ,  Sue Strang ,  Kurt Tallman ,  Youri Tretiakov

    IPC分类号： H02H9/00

    CPC分类号： H01L23/528 ,  H01L21/7684 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An critical interconnect line (300) for an integrated circuit is provided in which the problem of dishing of copper is addressed. An interconnect line (300) is provided for an integrated circuit in the form of a critical interconnect line modelled as a transmission line. The interconnect line (300) is formed of a conductive material having a width (302) and a length (303). The interconnect line (300) comprises at least two fingers (304, 305, 306) extending the length (303) of the interconnect line (300), an elongate aperture (309) in the conductive material separating two adjacent fingers (304, 305, 306), and one or more bridges (308) joining the fingers (304, 305, 306) at intervals along the length (303) of the interconnect line (300). The fingers (303, 304, 305) are kept within a width for which the effect of dishing acceptable width whilst the bridges (307, 308) keep the fingers (304, 305, 306) at the same potential difference.

    摘要翻译： 提供了一种用于集成电路的关键互连线（300），其中解决了铜的凹陷问题。 为以建模为传输线的关键互连线的形式的集成电路提供互连线（300）。 互连线（300）由具有宽度（302）和长度（303）的导电材料形成。 互连线（300）包括延伸互连线（300）的长度（303）的至少两个指状物（304,305,306），导电材料中的细长孔（309），分隔两个相邻的指状物（304,305 ，306）和沿着所述互连线（300）的长度（303）的间隔连接所述指状物（304,305,306）的一个或多个桥接器（308）。 手指（303,304,305）保持在一个宽度内，当桥接器（307,308）将手指（304,305,306）保持在相同的电位差时，凹槽可接受宽度的影响。