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561.发明申请MANUFACTURING METHOD OF POLYSILICON LAYER, AND POLYSILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权多晶硅层的制造方法和多晶硅薄膜晶体管及其制造方法公开(公告)号：US20150155390A1
公开(公告)日：2015-06-04
申请号：US14348699
申请日：2013-11-11
Inventor： Zuqiang Wang
IPC: H01L29/786 , H01L29/16 , H01L29/66 , H01L21/306 , H01L21/308 , H01L29/04 , H01L21/02
CPC classification number: H01L29/78672 , H01L21/02532 , H01L21/02592 , H01L21/02642 , H01L21/02645 , H01L21/02667 , H01L21/02675 , H01L21/02686 , H01L21/02694 , H01L21/30604 , H01L21/3081 , H01L21/3083 , H01L27/1277 , H01L27/1281 , H01L27/1288 , H01L29/04 , H01L29/16 , H01L29/6675
Abstract: A manufacturing method of a polysilicon layer and a manufacturing method of a polysilicon thin film transistor. The manufacturing method of the polysilicon layer includes: providing a substrate; forming a barrier layer and a buffer layer on the substrate; disposing a plurality of grooves in the buffer layer by a patterning process, and forming crystal seeds on the buffer layer; forming an amorphous silicon layer on the buffer layer provided with the grooves and on the crystal seeds; transferring the amorphous silicon layer into a polysilicon layer using a thermal treatment process.
Abstract translation: 多晶硅层的制造方法以及多晶硅薄膜晶体管的制造方法。 多晶硅层的制造方法包括：提供基板; 在衬底上形成阻挡层和缓冲层; 通过图案化工艺在缓冲层中设置多个槽，并在缓冲层上形成晶种; 在设置有凹槽的缓冲层上和晶体晶种上形成非晶硅层; 使用热处理工艺将非晶硅层转移到多晶硅层中。
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公开(公告)号：US12217718B2
公开(公告)日：2025-02-04
申请号：US18042194
申请日：2022-06-30
Inventor： Bo Zhao , Jianyun Xie , Jingyi Xu , Hui Yuan , Chao Liang , Guodong Wang , Biqi Li , Peirong Huo
IPC: G09G3/36
Abstract: A display substrate is provided, including a display substrate that includes a display area and a bezel area; a plurality of scanning signal lines; a gate driver circuit in the bezel area; a plurality of load compensation units in the bezel area, where the load compensation units are between the gate driver circuit and a plurality of pixel units; and a plurality of scanning signal lead wires in the bezel area. At least one load compensation unit includes a compensation capacitor including a first compensation capacitor electrode in a first conductive layer and a second compensation capacitor electrode in a semiconductor layer, and an orthographic projection of the first compensation capacitor electrode on the base substrate at least partially overlaps with an orthographic projection of the second compensation capacitor electrode on the base substrate. The first compensation capacitor electrode is electrically connected to a scanning signal lead wire.
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公开(公告)号：US20240355831A1
公开(公告)日：2024-10-24
申请号：US18039284
申请日：2021-12-28
Inventor： Jingyi XU , Jianyun XIE , Wei LI , Jian SUN , Zhen WANG , Yanqing CHEN , Yanfeng LI , Lin HOU , Aiyu DING , Jiantao LIU
IPC: H01L27/12
CPC classification number: H01L27/124
Abstract: Disclosed are a display substrate, a display substrate motherboard and a display apparatus. The display substrate includes a display region and a bonding region located on a side of the display region, wherein the bonding region includes a fanout region, the fanout region includes a first anti-static area and a first wiring area located around the first anti-static area, the first wiring area includes a plurality of fanout wires, the first anti-static area includes at least one electrostatic protection structure disposed between the plurality of fanout wires, and the electrostatic protection structure includes at least one pair of electrostatic protection lines, and the pair of electrostatic protection lines includes two electrostatic protection lines disposed symmetrically about a center line extending in a first direction.
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公开(公告)号：US20240353720A1
公开(公告)日：2024-10-24
申请号：US18028523
申请日：2022-03-31
Inventor： Peirong HUO , Chao LIANG , Peng LIU , Jingyi XU , Bo LI , Zhenhong XIAO
IPC: G02F1/1362
CPC classification number: G02F1/136286 , G02F1/136218
Abstract: An array substrate and a display device are provided. The array substrate includes a display area and a non-display area that at least partially surrounds the display area; the non-display area includes at least two clock signal lines, wherein a ratio of a spacing between two adjacent clock signal lines to a line width of the clock signal lines is greater than or equal to 3.
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公开(公告)号：US20240272499A1
公开(公告)日：2024-08-15
申请号：US18021943
申请日：2022-04-28
Inventor： Aiyu Ding , Jianyun Xie , Jingyi Xu , Yongqiang Zhang , Xize Chang , Wanzhi Chen
IPC: G02F1/1362 , G02F1/1339 , G02F1/1368
CPC classification number: G02F1/136286 , G02F1/1339 , G02F1/136209 , G02F1/136222 , G02F1/1368
Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a plurality of pixel regions, and each pixel region corresponds to a pixel. Each pixel region includes sub-regions in at least two rows, the sub-regions in each row include at least two sub-regions, a part of the sub-regions in each pixel region correspond to the sub-pixels of the pixel, and at least one sub-region is an opaque region.
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Patent Agency Ranking
公开(公告)号：US20240265836A1
公开(公告)日：2024-08-08
申请号：US18021590
申请日：2022-04-14
Inventor： Nini BAI , Yonghong ZHANG , Liangliang LIU
IPC: G09G3/00 , G09G3/3291
CPC classification number: G09G3/006 , G09G3/3291 , G09G2320/0233 , G09G2330/08 , G09G2330/10
Abstract: A method of repairing a display defect in a display panel includes: in a module process stage, inputting a first data voltage to each pixel in the display panel, enabling the display panel to display an image to be detected, and acquiring a brightness of each pixel; determining a reference pixel and a defect pixel according to the image to be detected; calculating a compensation data voltage for the defect pixel according to a brightness difference between the reference pixel and the defect pixel; and inputting the first data voltage to the reference pixel, and inputting a second data voltage to the defect pixel, according to the compensation data voltage, where the second data voltage is a sum of the first data voltage and the compensation data voltage.
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公开(公告)号：US20240233646A1
公开(公告)日：2024-07-11
申请号：US18618111
申请日：2024-03-27
Inventor： Qianqian ZHANG , Liangliang LIU , Zhiyong XUE , Liman PENG , Yan WU , Sihui DUAN , Le GAO
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2310/061 , G09G2320/0233
Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of sub-pixels located thereon. Each sub-pixel includes a pixel circuit and a pixel electrode electrically connected thereto, and each pixel circuit includes a driving sub-circuit. The pixel electrode includes a main electrode part and a first electrode extension part extending therefrom. The display substrate includes first type of sub-pixels. The main electrode part of each sub-pixel of the first type of sub-pixels is not overlapped with a control electrode of the driving sub-circuit of the sub-pixel or an electrode part directly electrically connected to the control electrode, and the first electrode extension part of each pixel electrode is at least partially overlapped with the control electrode or the electrode part. The first type of sub-pixels include at least two sub-pixels configured to emit light of different colors.
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公开(公告)号：US20240231163A1
公开(公告)日：2024-07-11
申请号：US17911491
申请日：2021-10-25
Inventor： Peirong HUO , Bo LI , Peng LIU , Yongqiang ZHANG , Jingyi XU
IPC: G02F1/1362 , G02F1/1368 , H01L27/12
CPC classification number: G02F1/136209 , G02F1/136286 , G02F1/1368 , H01L27/124
Abstract: The array base plate includes a plurality of sub-pixels that are arranged in an array; each of the sub-pixels includes a light shielding layer, a semiconductor layer, a grid layer, a source-drain layer and a pixel electrode layer that are arranged in layer configuration on the substrate sequentially; the semiconductor layer includes a first contacting part, a first channel part, a doping part, a second channel part and a second contacting part that are sequentially connected; the grid layer includes a first grid electrode and a second grid electrode; the source-drain layer includes a first electrode and a second electrode; and an orthographic projection of the light shielding layer on the substrate at least covers orthographic projections on the substrate of the first channel part, the second channel part and a part of the first contacting part.
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569.发明公开公开(公告)号：US20240222511A1
公开(公告)日：2024-07-04
申请号：US17907790
申请日：2021-09-29
Inventor： Haidong Su , Feng Li , Yezhou Fang , Lei Yao , Lei Yan , Chenglong Wang , Kai Li , Xiaogang Zhu , Hua Yang , Lin Hou , Yun Gao
IPC: H01L29/786 , H01L21/265 , H01L21/306 , H01L27/12 , H01L29/66
CPC classification number: H01L29/78621 , H01L29/66765 , H01L29/78669 , H01L21/26513 , H01L21/30604 , H01L27/1229
Abstract: Provided is an amorphous silicon thin-film transistor including an amorphous silicon semiconductor layer, a source electrode, and a drain electrode that are successively disposed on a base substrate. Ions doped by an ion implantation process are present in a region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer. A concentration of the ions in a surface region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer is greater than or equal to 5*10{circumflex over ( )}20 atoms/cc.
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公开(公告)号：US20240210772A1
公开(公告)日：2024-06-27
申请号：US18428784
申请日：2024-01-31
Inventor： Jingwei HOU , Jingyi XU , Yanwei REN , Wenlong ZHANG , Yanan YU , Lei JIA , Yanhao SUN , Guolei ZHI
IPC: G02F1/1362 , G02F1/1368 , G06F3/041
CPC classification number: G02F1/136254 , G02F1/136209 , G02F1/1368 , G06F3/0412
Abstract: An array substrate of a display device includes a pixel electrode layer on a substrate, which includes active pixel electrodes in an active display region; outermost active pixel electrodes include a first active pixel electrode including a first pixel electrode edge and a second pixel electrode edge; in a first direction, the first pixel electrode edge is between the second pixel electrode edge and a frame region. One of the array substrate and an opposite substrate of the display device includes a common electrode layer including a first extended common electrode which includes a first extended portion extending beyond the first active pixel electrode; a first extended portion edge of the first extended portion and a first substrate edge of the substrate respectively extend in a second direction; in the first direction, the first extended portion edge is located between the first substrate edge and the first pixel electrode edge.
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