公开(公告)号：US10725949B2

公开(公告)日：2020-07-28

申请号：US16115388

申请日：2018-08-28

申请人： QUALCOMM Incorporated

发明人： Sharon Graif ,  Lior Amarilio ,  Mark Gakman

IPC分类号： G06F13/362 ,  G06F13/42 ,  G06F1/32 ,  G06F1/10 ,  G06F1/3296 ,  G06F1/3293 ,  G06F1/3287

摘要： Methods and apparatuses for operating a direct communication over a serial communication bus are provided. An apparatus includes a master having a host controller. The host controller is configured to communicate with a first slave and with a second slave via a serial communication bus using at least one master-slave address, in accordance with a serial communication protocol. The host controller includes a master-slave module configured to operate communication with the first slave and with the second slave via the serial communication bus in accordance with the serial communication protocol and be in a low-power mode while the first slave and the second slave are in a direct communication. The host controller includes an always-on module configured to, while the master-slave module is in the low-power mode, clock the serial communication bus for the direct communication.

公开(公告)号：US20200225722A1

公开(公告)日：2020-07-16

申请号：US16648206

申请日：2018-01-25

申请人： Intel Corporation

发明人： CHEE LIM NGE ,  CHIA-HUNG KUO ,  NIVEDITA AGGARWAL ,  VENKATARAMANI GOPALAKRISHNAN ,  ROBERT GOUGH ,  BASAVARAJ ASTEKAR ,  VIJAYKUMAR KADGI

IPC分类号： G06F1/26 ,  G06F1/3293 ,  G06F13/42 ,  G06F9/4401

摘要： Apparatus and methods for managing power consumption of a data-path in a computer system are provided, the data-path comprising a first port and a second port, the first port comprising a high-speed and the second port comprising a low-speed port. The disclosed method including connecting a device to the data-path, determining that the connected device is to communicate using the second port and turning off an active circuit associated with the first port of the data-path.

公开(公告)号：US10712831B2

公开(公告)日：2020-07-14

申请号：US16333037

申请日：2017-10-13

申请人： SONY CORPORATION

发明人： Kei Takahashi

IPC分类号： G06F3/044 ,  G06F3/01 ,  G06F1/28 ,  G06F1/3293 ,  G06F1/16 ,  H04R1/10

摘要： When first sensor information is input to an information processing unit in an information processing apparatus, the information processing unit detects a trigger operation according to a type of the first sensor information. Moreover, the information processing unit recognizes a gesture operation by a user as an operation input on the basis of second sensor information operation. In addition, the information processing unit determines the operation input on the basis of a combination of the detected trigger operation and the recognized gesture operation. According to the information processing apparatus, it is possible that the operation input is diversified without imposing a burden on the user.

公开(公告)号：US10684670B2

公开(公告)日：2020-06-16

申请号：US16390998

申请日：2019-04-22

申请人： Apple Inc.

发明人： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC分类号： G06F9/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

摘要： Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20200150745A1

公开(公告)日：2020-05-14

申请号：US16746121

申请日：2020-01-17

申请人： Apple Inc.

发明人： Anand Dalal ,  Joshua P. de Cesare

IPC分类号： G06F1/3287 ,  G06F1/3293 ,  G06F1/3231 ,  G06F1/3215 ,  G06F1/3209 ,  G06F9/4401

摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

公开(公告)号：US10649935B2

公开(公告)日：2020-05-12

申请号：US16195478

申请日：2018-11-19

申请人： Apple Inc.

发明人： Derek R. Kumar ,  Joshua Phillips de Cesare

IPC分类号： G06F13/24 ,  G06F1/3293 ,  G06F9/4401

摘要： A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

公开(公告)号：US10649516B2

公开(公告)日：2020-05-12

申请号：US15477185

申请日：2017-04-03

申请人： CANON KABUSHIKI KAISHA

发明人： Shigeki Hasui

IPC分类号： G06F1/32 ,  H04L12/12 ,  G06F1/3203 ,  H04L29/06 ,  H04L12/10 ,  G06F1/3293 ,  G06F1/3287 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/26 ,  G06F3/12 ,  G06F21/81 ,  H04L12/24 ,  H04N1/00

摘要： An information processing apparatus that can avoid an IEEE802.1X re-authentication process due to a communication speed setting change made at the time of transitioning to the power-saving state and realize both of security and power-saving. Fixed link speed with which both a MFP 100 and a communication apparatuses are compatible is set on the basis of acquired pieces of link speed setting information about the MFP 100 and the communication apparatus. Then, 100 Mbps lower than 1000 Mbps is fixedly set on the basis of acquired power-saving setting information about the MFP 100 when the power-saving setting is effective, and EEE is enabled.

公开(公告)号：US10571992B2

公开(公告)日：2020-02-25

申请号：US15634805

申请日：2017-06-27

申请人： INTEL CORPORATION

发明人： Robert E. Gough ,  Mazen G. Gedeon ,  Barnes Cooper ,  Basavaraj B. Astekar ,  Sean C. Dardis

IPC分类号： G06F1/32 ,  G06F1/3234 ,  G06F1/3231 ,  G06F1/3293

摘要： An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.

公开(公告)号：US10551906B2

公开(公告)日：2020-02-04

申请号：US16133543

申请日：2018-09-17

申请人： Apple Inc.

发明人： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC分类号： G06F13/12 ,  G06F12/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

摘要： Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US10536902B2

公开(公告)日：2020-01-14

申请号：US16357178

申请日：2019-03-18

申请人： Apple Inc.

发明人： Hugo Fiennes

IPC分类号： H04M1/00 ,  H04W52/02 ,  H04W24/08 ,  H04W76/38 ,  G06F1/3296 ,  G06F1/3293 ,  H04W80/02

摘要： Mobile devices such as cellular telephones are provided that communicate with wireless networks. Cellular telephone network equipment may communicate with a cellular telephone over a data connection. The cellular telephone may have an internet protocol (IP) address that allows data to be provided to the cellular telephone over the data connection. To conserve resources and release unused IP addresses, the cellular telephone network equipment may deactivate inactive data connections after a period of inactivity. A baseband processor within a mobile device may periodically send User Datagram Protocol (UDP) keep-alive packets over the data connection to ensure that the data connection remains active. The keep-alive packets may be directed to a packet sink server or may be associated with a black hole route. An applications processor in the telephone may remain in sleep mode during keep-alive packet transmission to conserve power.