公开(公告)号：US20160077987A1

公开(公告)日：2016-03-17

申请号：US14867770

申请日：2015-09-28

Applicant: Apple Inc.

Inventor： Derek R. Kumar ,  Joshua Phillips de Cesare

IPC: G06F13/24 ,  G06F9/44 ,  G06F1/32

CPC classification number: G06F13/24 ,  G06F1/3293 ,  G06F9/4418 ,  Y02D10/14

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred WI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract translation: 在一个实施例中，数据处理系统包括至少第一处理器和第二处理器以及中断控制器，并且系统提供延迟的处理器间中断（IPI），其可用于将第二处理器从低 电力睡眠状态。 在一个实施例中，延迟IPI在中断控制器中被定时器延迟，并且如果第一处理器变得可用于执行可由触发延迟的中断的线程可用的线程，则延迟WI可被第一处理器取消 IPI。

公开(公告)号：US10152438B2

公开(公告)日：2018-12-11

申请号：US14867770

申请日：2015-09-28

Applicant: Apple Inc.

Inventor： Derek R. Kumar ,  Joshua Phillips de Cesare

IPC: G06F13/24 ,  G06F1/32 ,  G06F9/4401

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

公开(公告)号：US20190155770A1

公开(公告)日：2019-05-23

申请号：US16195478

申请日：2018-11-19

Applicant: Apple Inc.

Inventor： Derek R. Kumar ,  Joshua Phillips de Cesare

IPC: G06F13/24 ,  G06F9/4401 ,  G06F1/3293

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (WI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred WI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

公开(公告)号：US10649935B2

公开(公告)日：2020-05-12

申请号：US16195478

申请日：2018-11-19

Applicant: Apple Inc.

Inventor： Derek R. Kumar ,  Joshua Phillips de Cesare

IPC: G06F13/24 ,  G06F1/3293 ,  G06F9/4401

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

公开(公告)号：US09208113B2

公开(公告)日：2015-12-08

申请号：US13741811

申请日：2013-01-15

Applicant: Apple Inc.

Inventor： Derek R. Kumar ,  Joshua Phillips de Cesare

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F1/3293 ,  G06F9/4418 ,  Y02D10/14

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract translation: 在一个实施例中，数据处理系统包括至少第一处理器和第二处理器以及中断控制器，并且系统提供延迟的处理器间中断（IPI），其可用于将第二处理器从低 电力睡眠状态。 在一个实施例中，延迟IPI在中断控制器中被定时器延迟，并且如果第一处理器变得可用于执行由可触发延迟的中断而导致的线程可用的线程可以被第一处理器取消延迟IPI IPI。

公开(公告)号：US20140201411A1

公开(公告)日：2014-07-17

申请号：US13741811

申请日：2013-01-15

Applicant: APPLE INC.

Inventor： Derek R. Kumar ,  Joshua Phillips de Cesare

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F1/3293 ,  G06F9/4418 ,  Y02D10/14

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract translation: 在一个实施例中，数据处理系统包括至少第一处理器和第二处理器以及中断控制器，并且系统提供延迟的处理器间中断（IPI），其可用于将第二处理器从低 电力睡眠状态。 在一个实施例中，延迟IPI在中断控制器中被定时器延迟，并且如果第一处理器变得可用于执行由可触发延迟的中断而导致的线程可用的线程可以被第一处理器取消延迟IPI IPI。