公开(公告)号：US08432206B2

公开(公告)日：2013-04-30

申请号：US13425379

申请日：2012-03-20

Applicant: Der-Min Yuan ,  Kuang-Fu Teng ,  Chun Shiah ,  Feng-Chia Chang

Inventor： Der-Min Yuan ,  Kuang-Fu Teng ,  Chun Shiah ,  Feng-Chia Chang

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L1/02

Abstract: A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.

Abstract translation: 延迟锁定环路系统包括时序控制器，或门，输入缓冲器，脉冲发生器和延迟锁定环。 定时控制器用于在省电信号处于逻辑低电压的同时周期性地输出外部使能信号，并且根据省电信号的逻辑高电压被禁用。 脉冲发生器用于根据省电信号的上升沿产生脉冲。 OR门耦合到定时控制器，用于接收功率节省信号，脉冲和外部使能信号，并根据功率节省信号和外部使能信号输出使能信号。 延迟锁定环路被耦合到或门和输入缓冲器，以根据使能信号再次启用延迟锁定环路。

公开(公告)号：US20130038397A1

公开(公告)日：2013-02-14

申请号：US13568129

申请日：2012-08-07

Applicant: KAORU KOBAYASHI

Inventor： KAORU KOBAYASHI

IPC: H03K3/03

CPC classification number: H03L1/02

Abstract: An oscillation device for reducing memory capacity includes a frequency difference detecting unit and a compensation value obtaining unit. When oscillation frequencies of the first and second oscillation circuits are respectively f1 and f2, and oscillation frequencies of the first and second oscillation circuits at a reference temperature are respectively f1r and f2r, the frequency difference detecting unit determines a difference corresponding value x corresponding to a difference value between a value corresponding to a difference between f1 and f1r, and a value corresponding to a difference between f2 and f2r. The compensation value obtaining unit obtains a frequency compensation value of f1 resulting from ambient temperature different from reference temperature based on the difference corresponding value x, and calculates the frequency compensation value of f1 by calculating nth-order polynomial for X being a value corresponding to x/k, where k is a divide coefficient specific to a device.

Abstract translation: 用于降低存储容量的振荡装置包括频率差检测单元和补偿值获取单元。 当第一和第二振荡电路的振荡频率分别为f1和f2，第一和第二振荡电路在参考温度下的振荡频率分别为f1r和f2r时，频差检测单元确定对应于 在与f1和f1r之间的差对应的值之间的差值以及与f2和f2r之间的差对应的值。 补偿值获取单元基于差值对应值x从与参考温度不同的环境温度获得f1的频率补偿值，并且通过计算X的频率补偿值，计算对应于x的值的n阶多项式 / k，其中k是特定于设备的分频系数。

公开(公告)号：US20120256666A1

公开(公告)日：2012-10-11

申请号：US13425379

申请日：2012-03-20

Applicant: Der-Min Yuan ,  Kuang-Fu Teng ,  Chun Shiah ,  Feng-Chia Chang

Inventor： Der-Min Yuan ,  Kuang-Fu Teng ,  Chun Shiah ,  Feng-Chia Chang

IPC: H03L7/08

CPC classification number: H03L7/0812 ,  H03L1/02

Abstract: A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.

Abstract translation: 延迟锁定环路系统包括时序控制器，或门，输入缓冲器，脉冲发生器和延迟锁定环。 定时控制器用于在省电信号处于逻辑低电压的同时周期性地输出外部使能信号，并且根据省电信号的逻辑高电压被禁用。 脉冲发生器用于根据省电信号的上升沿产生脉冲。 OR门耦合到定时控制器，用于接收功率节省信号，脉冲和外部使能信号，并根据功率节省信号和外部使能信号输出使能信号。 延迟锁定环路被耦合到或门和输入缓冲器，以根据使能信号再次启用延迟锁定环路。

公开(公告)号：US20110267150A1

公开(公告)日：2011-11-03

申请号：US12770230

申请日：2010-04-29

Applicant: Yongping Fan ,  Jing Li ,  Ian A. Young

Inventor： Yongping Fan ,  Jing Li ,  Ian A. Young

IPC: H03J7/04

CPC classification number: H03L1/02 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1234 ,  H03B5/124 ,  H03B5/1265 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/103 ,  H03L7/18

Abstract: A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

Abstract translation: 公开了用于LC-PLL系统中的自动频率控制和数字温度补偿的混合信号电路架构。 一些实施例允许诸如微处理器和芯片组的产品的大量制造以及采用LC-PLL技术的其它电路。 在一些实施例中，可以选择各种电容器负载以补偿与过程，电压，温度和参考频率相关联的变化。 此外，根据一些实施例，可以选择性地使用多支脚电容器组来进一步补偿温度变化后锁定。 在一些实施例中可以使用可编程定时器，以便在评估感兴趣的参数之前允许循环结算。

公开(公告)号：US20110221490A1

公开(公告)日：2011-09-15

申请号：US12931779

申请日：2011-02-10

Applicant: Hiroki Kimura

Inventor： Hiroki Kimura

IPC: H03L7/08

CPC classification number: H03L7/14 ,  H03L1/02

Abstract: There is provided an art to prevent an unstable operation due to temperature in a PLL apparatus in which a proper range of an amplitude level of an external reference frequency signal is specified and a control voltage is supplied to a voltage-controlled oscillator according to whether the amplitude level falls within the proper range or not. The PLL apparatus includes: a switching unit switching a signal that is to be supplied to a control voltage output unit between a signal of a phase comparison unit and a preset signal of a preset signal output unit; a protection circuit provided between a signal path of a reference frequency signal and a ground and having diodes that are connected in inverse parallel in order to regulate an amplitude level of the reference frequency signal; a temperature detection unit detecting an atmospheric temperature of the protection circuit; and a level detection unit detecting the amplitude level of the external reference frequency signal, and threshold values as references for the switching are set according to the detected temperature, thereby coping with a change in the amplitude level due to a temperature characteristic of the diodes.

Abstract translation: 提供了一种防止在PLL装置中由于温度导致的不稳定操作的技术，其中指定了外部参考频率信号的幅度电平的适当范围，并且根据是否将控制电压提供给压控振荡器 振幅水平落在适当的范围内。 PLL装置包括：切换单元，将要提供给控制电压输出单元的信号切换到相位比较单元的信号和预设信号输出单元的预置信号之间; 保护电路，其设置在基准频率信号的信号路径与地之间，具有并联连接的二极管，以便调节参考频率信号的振幅电平; 温度检测单元，检测保护电路的大气温度; 检测外部参考频率信号的振幅电平的电平检测单元，根据检测到的温度设定作为开关用的参考值的阈值，从而应对由二极管的温度特性引起的振幅电平的变化。

公开(公告)号：US07884655B2

公开(公告)日：2011-02-08

申请号：US12346297

申请日：2008-12-30

Applicant: Walter Marton ,  Bernrd Germann

Inventor： Walter Marton ,  Bernrd Germann

IPC: H03L7/06

CPC classification number: H03L7/18 ,  H03L1/02 ,  H03L5/00 ,  H03L7/10 ,  H03L7/193 ,  H03L7/1976 ,  H03L2207/06

Abstract: Control circuitry, comprising: first control means operable to generate a first control signal, the first control signal being indicative of a relationship between an output signal and a first reference signal, and to generate said output signal in dependence upon said first control signal, the first control means being configured to tend to maintain a first desired relationship between the output signal and the first reference signal in response to said first control signal; and second control means configured to influence operation of said first control means in response to said first control signal by way of a second control signal so as to tend to maintain a second desired relationship between said first control signal and a second reference signal.

Abstract translation: 控制电路，包括：第一控制装置，可操作以产生第一控制信号，所述第一控制信号指示输出信号和第一参考信号之间的关系，并且根据所述第一控制信号产生所述输出信号， 第一控制装置被配置为响应于所述第一控制信号趋向于保持输出信号和第一参考信号之间的第一期望关系; 以及第二控制装置，被配置为响应于所述第一控制信号通过第二控制信号影响所述第一控制装置的操作，以便趋向于保持所述第一控制信号和第二参考信号之间的第二期望关系。

公开(公告)号：US20100182062A1

公开(公告)日：2010-07-22

申请号：US12412936

申请日：2009-03-27

Applicant: Gautham Devendra Kamath ,  Jeff W. Baumgartner ,  John Christopher Tucker

Inventor： Gautham Devendra Kamath ,  Jeff W. Baumgartner ,  John Christopher Tucker

IPC: H03L7/00

CPC classification number: G06F17/00 ,  H03H17/0628 ,  H03L1/02

Abstract: An integrated circuit audio processor having an internal-oscillator generated intermediate frequency reference provides for operation of an audio processor without requiring an external master clock. Input audio streams are sample-rate converted to an intermediate sample rate derived from the internal oscillator, which may be an LC oscillator. One or more output audio streams are generated from the one or more input audio streams at the intermediate sample rate and are converted from the intermediate sample rate to corresponding output sample rates. A divider generates the intermediate sample rate from the oscillator output, and is programmed to control the intermediate sample rate to ensure that the intermediate sample rate is in the proper range for operation of the integrated circuit. The divider can be programmed to accommodate changes in process, voltage and/or temperature of the IC, so that the intermediate sample rate is maintained near an expected frequency.

Abstract translation: 具有内部振荡器产生的中频参考的集成电路音频处理器提供音频处理器的操作而不需要外部主时钟。 输入音频流被采样率转换成从内部振荡器得到的中间采样速率，内部振荡器可以是LC振荡器。 从中间采样率的一个或多个输入音频流产生一个或多个输出音频流，并从中间采样率转换为对应的输出采样率。 分压器从振荡器输出产生中间采样率，并且被编程为控制中间采样率，以确保中间采样率在集成电路的操作的适当范围内。 分频器可以被编程以适应IC的过程，电压和/或温度的变化，使得中间采样率保持在预期频率附近。

公开(公告)号：US07720469B2

公开(公告)日：2010-05-18

申请号：US11321331

申请日：2005-12-29

Applicant: Erik Olaf Kerstenbeck

Inventor： Erik Olaf Kerstenbeck

IPC: H04M11/00

CPC classification number: H03L1/02 ,  H03L7/00 ,  H04L27/0014 ,  H04L2027/0016

Abstract: A wireless telecommunication device, a method of frequency calibrating a wireless telecommunication device, and a computer program are provided. The method comprises: receiving a reference radio signal of the wireless telecommunications system; frequency synchronizing the wireless telecommunication device with the reference radio signal by adjusting a control parameter controlling a reference frequency generated by a reference frequency generator; measuring a temperature parameter characterizing the temperature of the reference frequency generator; and generating calibration information for calibrating the wireless telecommunication device on the basis of the control parameter and the temperature parameter.

Abstract translation: 提供无线电信设备，频率校准无线电信设备的方法和计算机程序。 该方法包括：接收无线电信系统的参考无线电信号; 通过调整控制由参考频率发生器产生的参考频率的控制参数，使无线电信设备与参考无线电信号同步; 测量表征参考频率发生器温度的温度参数; 以及根据控制参数和温度参数生成用于校准无线电信设备的校准信息。

公开(公告)号：US07714674B2

公开(公告)日：2010-05-11

申请号：US11967372

申请日：2007-12-31

Applicant: Xiaoling Guo ,  Alan L. Westwick

Inventor： Xiaoling Guo ,  Alan L. Westwick

IPC: H03L1/00

CPC classification number: H03L1/02

Abstract: The integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A real time clock circuit provides a system clock for the processing core. The real time clock further comprises an internal oscillator that generates the system clock for the integrated circuit package. The internal oscillator has a factory calibrated bias current. An internal oscillator control register controls the operation of the internal oscillator responsive to control bits of the programmable load capacitor array controlled by the processing core.

Abstract translation: 集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。 实时时钟电路为处理核心提供系统时钟。 实时时钟还包括产生用于集成电路封装的系统时钟的内部振荡器。 内部振荡器具有出厂校准的偏置电流。 响应于由处理核心控制的可编程负载电容阵列的控制位，内部振荡器控制寄存器控制内部振荡器的操作。

公开(公告)号：US20100085096A1

公开(公告)日：2010-04-08

申请号：US12360953

申请日：2009-01-28

Applicant: Nicholas H. SCHUTT ,  Karl F. GREB

Inventor： Nicholas H. SCHUTT ,  Karl F. GREB

IPC: H03L7/00

CPC classification number: H03L1/02

Abstract: A system comprises first timing logic configured to produce a first signal and second timing logic configured to produce a second signal. The system also comprises processing logic coupled to the first and second timing logic. The system further comprises clock logic that determines elapsed time using the first signal. The processing logic compares the first and second signals and, based on the comparison, the system adjusts the elapsed time.

Abstract translation: 系统包括被配置为产生第一信号的第一定时逻辑和被配置为产生第二信号的第二定时逻辑。 该系统还包括耦合到第一和第二定时逻辑的处理逻辑。 系统还包括使用第一信号确定经过时间的时钟逻辑。 处理逻辑比较第一和第二信号，并且基于比较，系统调整经过的时间。