公开(公告)号：US08345500B2

公开(公告)日：2013-01-01

申请号：US12912748

申请日：2010-10-27

申请人： Shih-Hsing Wang ,  Der-Min Yuan

发明人： Shih-Hsing Wang ,  Der-Min Yuan

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/006 ,  G11C29/1201 ,  G11C29/832

摘要： A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix.

摘要翻译： 具有禁用电路的存储器包括存储器矩阵和禁用电路。 存储器矩阵包括数据输入/输出端和输出使能端。 禁用电路包括保险丝和输出端。 当保险丝不熔断时，禁用电路根据输出使能端的信号将数据输入/输出端的信号发送到输出端。 当保险丝熔断时，禁用电路在输出端产生三态。 因此，外部电路不能执行读取或写入操作以访问存储器矩阵。

公开(公告)号：US08154940B2

公开(公告)日：2012-04-10

申请号：US12901569

申请日：2010-10-10

申请人： Der-Min Yuan

发明人： Der-Min Yuan

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C11/406 ,  G11C8/08 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4068

摘要： The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

摘要翻译： 本发明提供了一种在自刷新模式和相关存储器中减少存储器的电流的方法。 存储器包括字线驱动器和控制器，并且字线驱动器包括晶体管。 晶体管具有控制端子，耦合到字线的第一端子和第二端子。 该方法包括：在存储器进入自刷新模式之后：在自刷新操作期间控制控制终端与第二终端之间的电压差对应于第一值; 以及在非自刷新操作期间，控制所述控制端子与所述第二端子之间的电压差对应于小于所述第一值的第二值。

公开(公告)号：US20120063254A1

公开(公告)日：2012-03-15

申请号：US13024301

申请日：2011-02-09

申请人： Chun-Ching Hsia ,  Yen-An Chang ,  Der-Min Yuan

发明人： Chun-Ching Hsia ,  Yen-An Chang ,  Der-Min Yuan

IPC分类号： G11C5/14

CPC分类号： G11C5/147

摘要： A voltage regulator includes a first transistor, a second transistor, a third transistor, a feedback unit, a comparison unit, a first control unit and a second control unit. The first transistor is controlled by the feedback unit and the comparison unit, for stabilizing the voltage of the output node. When the first control unit turns on the second transistor, the voltage of the output node rises. When the first control unit turns off the second transistor, it triggers the second control unit turning on the third transistor, so the first transistor is turned on completely. Therefore, when the third transistor is turned off, the first transistor can be controlled by the feedback unit and the comparison unit for stabilizing the voltage of the output node.

摘要翻译： 电压调节器包括第一晶体管，第二晶体管，第三晶体管，反馈单元，比较单元，第一控制单元和第二控制单元。 第一晶体管由反馈单元和比较单元控制，用于稳定输出节点的电压。 当第一控制单元接通第二晶体管时，输出节点的电压升高。 当第一控制单元关闭第二晶体管时，它触发第二控制单元接通第三晶体管，因此第一晶体管完全导通。 因此，当第三晶体管截止时，可以通过反馈单元和比较单元来控制第一晶体管，以稳定输出节点的电压。

公开(公告)号：US07983102B2

公开(公告)日：2011-07-19

申请号：US12579920

申请日：2009-10-15

申请人： Shih-Hsing Wang ,  Der-Min Yuan ,  Bor-Doou Rong ,  Chun Shiah

发明人： Shih-Hsing Wang ,  Der-Min Yuan ,  Bor-Doou Rong ,  Chun Shiah

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/08

摘要： A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.

摘要翻译： 在本发明的实施例中公开了一种数据检测装置和数据检测方法。 数据检测装置根据具有预定周期的时钟信号进行操作。 数据检测装置包括多个存储单元，多个数据线，多个位线，多个读出放大器和预充电控制电路。

公开(公告)号：US20100171509A1

公开(公告)日：2010-07-08

申请号：US12548828

申请日：2009-08-27

申请人： Der-Min YUAN ,  Ming-Cheng Liang ,  Kuo-Hua Lee

发明人： Der-Min YUAN ,  Ming-Cheng Liang ,  Kuo-Hua Lee

IPC分类号： G01R31/02

CPC分类号： G01R31/31921 ,  G11C29/40

摘要： The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.

摘要翻译： 本发明公开了一种提高测试吞吐量的芯片测试电路。 芯片测试电路使用多路复用器在数据压缩基础单元之间切换数据压缩电路的连接，压缩基站单元压缩4个XIO，以便通过单个接口电路获得测试数据的多路复用器，并提高测试吞吐量。

公开(公告)号：US20080048727A1

公开(公告)日：2008-02-28

申请号：US11808865

申请日：2007-06-13

申请人： Der-Min Yuan ,  Shih-Hsing Wang

发明人： Der-Min Yuan ,  Shih-Hsing Wang

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/065 ,  G11C7/1051 ,  G11C7/1087 ,  G11C11/4091 ,  G11C11/4093

摘要： A sense amplifier-based latch is provided. It comprises an input circuit, a sense amplifier, a latch circuit and an output circuit. By employing the latch circuit, the variation frequency of an output signal and a complementary output signal as well as lots of charge consumption is reduced. Accordingly, the invention has less glitches and malfunctions, thus suitable for high-speed circuit applications.

摘要翻译： 提供基于读出放大器的锁存器。 它包括输入电路，读出放大器，锁存电路和输出电路。 通过采用锁存电路，减少了输出信号和互补输出信号的变化频率以及大量的电荷消耗。 因此，本发明具有较少的毛刺和故障，因此适用于高速电路应用。

公开(公告)号：US20070268062A1

公开(公告)日：2007-11-22

申请号：US11434812

申请日：2006-05-17

申请人： Der-Min Yuan ,  Ming Hung Wang

发明人： Der-Min Yuan ,  Ming Hung Wang

IPC分类号： H01H37/76

CPC分类号： G11C17/18

摘要： A fuse circuit for repair and detection includes a fuse resistor, a reference resistor, a voltage sensing circuit, an OP amplifier and a latch circuit. The resistance difference is correctly sensed by means of the voltage sensing circuit and the OP amplifier according to a voltage difference. Hence, whether the fuse resistor is programmed or not is accurately detected by the logic level of the output signal.

摘要翻译： 用于修理和检测的熔丝电路包括熔丝电阻，参考电阻，电压感测电路，OP放大器和锁存电路。 根据电压差，通过电压检测电路和OP放大器正确检测电阻差。 因此，是否通过输出信号的逻辑电平精确地检测到熔丝电阻是否被编程。

公开(公告)号：US06934899B2

公开(公告)日：2005-08-23

申请号：US10060481

申请日：2002-01-30

申请人： Der-Min Yuan ,  Bor-Doou Rong

发明人： Der-Min Yuan ,  Bor-Doou Rong

IPC分类号： G11C29/14 ,  G01R31/28 ,  G11C29/00

CPC分类号： G11C29/12015 ,  G11C11/401 ,  G11C29/14

摘要： In accordance with the objectives of the invention a new method is provided for testing DRAM cells using a slow-speed tester. An adjustable self-time scheme is provided that is used for write-recovery during the testing of DRAM devices using a low-speed tester. CSL and WL pulses are self-time controlled and are in this manner used to emulate DRAM operation under different operational conditions. The adjustable self-time scheme of the invention can be used to screen write recovery (twr) depending on field requirements for the DRAM cell, a low-speed tester can be used for the screening.

摘要翻译： 根据本发明的目的，提供了一种使用慢速测试仪测试DRAM单元的新方法。 提供了一种可调节的自身时间方案，用于使用低速测试仪测试DRAM器件时的写恢复。 CSL和WL脉冲是自我时间控制的，并且以这种方式用于在不同的操作条件下模拟DRAM操作。 根据DRAM单元的场要求，可以使用本发明的可调节自定时方案来屏蔽写恢复（twr），可以使用低速测试器进行筛选。

公开(公告)号：US20110026352A1

公开(公告)日：2011-02-03

申请号：US12901569

申请日：2010-10-10

申请人： Der-Min Yuan

发明人： Der-Min Yuan

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C8/08 ,  G11C11/40615 ,  G11C11/4085 ,  G11C2211/4068

摘要： The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

公开(公告)号：US20100026372A1

公开(公告)日：2010-02-04

申请号：US12353247

申请日：2009-01-13

申请人： Yen-An Chang ,  Der-Min Yuan

发明人： Yen-An Chang ,  Der-Min Yuan

IPC分类号： H03K17/687

CPC分类号： H03K17/687 ,  H03K2217/0036

摘要： A low-voltage power switch includes a gate-controlled circuit and a switch. The gate-controlled circuit generates a control voltage lower than the voltage of ground according to a control signal. The switch includes a first end, a second end, and a control end. The first end of the switch is coupled to a power supply of a low voltage, the control end of the switch is coupled to the gate-controlled circuit for receiving the gate-controlled signal, and the second end of the switch couples the first end of the switch when the switch receives the gate-controlled signal for outputting the power supply of the low voltage.

摘要翻译： 低压电源开关包括门控电路和开关。 栅极控制电路根据控制信号产生低于接地电压的控制电压。 开关包括第一端，第二端和控制端。 开关的第一端耦合到低电压的电源，开关的控制端耦合到栅极控制电路以接收栅极控制的信号，并且开关的第二端将第一端 当开关接收用于输出低电压电源的栅极控制信号时，