公开(公告)号：US5081627A

公开(公告)日：1992-01-14

申请号：US375899

申请日：1989-07-05

Applicant: Hong Yu

Inventor： Hong Yu

IPC: G06F11/25 ,  G06F11/267 ,  G06F11/30 ,  G06F11/32 ,  H04L12/26

CPC classification number: G06F11/2221 ,  H04L12/2602 ,  H04L43/00 ,  G06F11/25 ,  G06F11/328

Abstract: Diagnostic monitoring apparatus for connection in-line with a cable connecting a first device to a second device and carrying binary information between the first device and the second device over a wire contained in the cable. There is a series connector inserting a connecting wire in series with the wire in the cable. Signal sampling and triggering logic is connected to the connecting wire for sensing any binary signals on the connecting wire and for producing a trigger output when a binary signal is sensed. There is also an illuminatable visible indicator in the form of an LED and a monostable device having the trigger output connected to an input thereof and an output connected to the indicator for producing a signal at the output of sufficient duration to illuminate the indicator for a visibly detectable period of time. The high speed signal sampling and triggering logic is high impedance and connected in parallel to the connecting wire whereby the signal in the wire in the cable is not loaded down. Typically, the cable being monitored is a multi-wire cable and power is derived from one of the wires in the cable. In a contention LAN, the device monitors and displays activity associated with transmit, receive, and collision functions.

Abstract translation: 用于连接与将第一设备连接到第二设备并且通过电缆中包含的电线在第一设备和第二设备之间承载二进制信息的电缆的诊断监视设备。 有一个串联连接器将连接线与电缆中的导线串联。 信号采样和触发逻辑连接到连接线，用于感测连接线上的任何二进制信号，并在感测到二进制信号时产生触发输出。 还有一种LED的可见可见指示器和单稳态器件，其触发输出连接到其输入端，输出端连接到指示器，用于在足够的持续时间的输出处产生一个信号，以便可见地照亮指示器 可检测的时间段。 高速信号采样和触发逻辑是高阻抗并联连接到连接线，因此电缆中的信号中的信号没有被加载下来。 通常，被监测的电缆是多线电缆，并且电力源自电缆中的一条电线。 在争用局域网中，设备监视和显示与发送，接收和冲突功能相关的活动。

公开(公告)号：US5073968A

公开(公告)日：1991-12-17

申请号：US230807

申请日：1988-08-09

Applicant: Robert D. Morrison

Inventor： Robert D. Morrison

IPC: G06F11/28 ,  G06F11/22 ,  G06F11/25 ,  G06F11/26 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/261 ,  G06F11/348 ,  G06F11/25

Abstract: Additional memory for holding marking tags is used for providing additional information regarding states acquired by an emulator during tracing for dequeueing. The marking tags are determined according to a predetermined coding scheme, loaded in a marking memory, and acquired during tracing along with the fetched instruction states. The combination of addresses, data, status, and the additional marking tags is converted into a list of states which correspond to the test program executed by the target processor means.

公开(公告)号：US4821269A

公开(公告)日：1989-04-11

申请号：US922367

申请日：1986-10-23

Applicant: Richard A. Jackson ,  David E. Lake, Jr. ,  James E. Blecksmith ,  Ronnie D. Barnett ,  John Abt

Inventor： Richard A. Jackson ,  David E. Lake, Jr. ,  James E. Blecksmith ,  Ronnie D. Barnett ,  John Abt

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/25 ,  G06F11/00

CPC classification number: G01R31/318505 ,  G06F11/22 ,  G06F11/25

Abstract: A diagnostic system for a digital signal processor, having an input module, an output module and a plurality of successive processing modules defining a signal processing path, monitors various internal test points within each module. Any one of the test points may be connected to a diagnostic bus. The output of the diagnostic bus may be appropriately modified and input to the output module in lieu of the digital signal from the last processing module to provide a diagnostic display.

Abstract translation: 一种用于数字信号处理器的诊断系统，具有输入模块，输出模块和定义信号处理路径的多个连续的处理模块，监视每个模块内的各种内部测试点。 任何一个测试点可以连接到诊断总线。 可以适当地修改诊断总线的输出并将其输入到输出模块以代替来自最后处理模块的数字信号以提供诊断显示。

公开(公告)号：US4813009A

公开(公告)日：1989-03-14

申请号：US667687

申请日：1984-11-02

Applicant: James L. Tallman

Inventor： James L. Tallman

IPC: G06F11/25 ,  G06F11/34 ,  G06F11/36 ,  G06F9/00

CPC classification number: G06F11/3636 ,  G06F11/3466 ,  G06F11/25 ,  G06F11/36

Abstract: An improved method and apparatus is disclosed for determining the internal state of a processor without disturbing the operational environment of the processor. A two phase process is employed. In the first phase, external signals produced by the processor in the execution of a known program are monitored and recorded for subsequent analysis. In the second phase, the recorded information is analyzed in the light of the known characteristic of the processor, the program it was executing, and the signals recorded during the first phase. The internal state of the processor is thereby determined after the execution of each instruction. In addition, provisions are made for the specification of breakpoints, and the examination of simulated status of the processor on the occurrence of the breakpoints.

Abstract translation: 公开了一种用于确定处理器的内部状态而不干扰处理器的操作环境的改进的方法和装置。 采用两相工艺。 在第一阶段中，监视和记录由处理器在执行已知程序中产生的外部信号用于后续分析。 在第二阶段，根据处理器的已知特性，正在执行的程序以及在第一阶段记录的信号来分析所记录的信息。 因此，在每个指令的执行之后确定处理器的内部状态。 另外还规定了断点的规定，以及对发生断点处理器的模拟状态的检查。

公开(公告)号：US4731768A

公开(公告)日：1988-03-15

申请号：US906873

申请日：1986-09-15

Applicant: John L. Easterday

Inventor： John L. Easterday

IPC: G01R13/28 ,  G06F11/25 ,  G06F11/34 ,  G04F8/00 ,  G01R23/02

CPC classification number: G06F11/348 ,  G06F11/25

Abstract: A time stamp circuit comprises a plurality of counter programmable logic arrays for providing a Gray code count. Each count provided by the counters is associated as a time value with a specified event to be stored in memory. The count is generated automatically over a range of progressively slower frequencies provided by frequency dividing circuitry connected to an oscillator. The circuit has two modes of operation, a cumulative mode and a delta mode. In the cumulative mode, the count begins with the first occurrence of a specified event and ends when acquisition is halted. In the delta mode, a control programmable logic array automatically resets the Gray code count and thereby the clock frequency to its highest frequency each time a specified event is stored. The resolution, or time between counts, therefore is the same to begin between each pair of events.

Abstract translation: 时间戳电路包括用于提供格雷码计数的多个计数器可编程逻辑阵列。 由计数器提供的每个计数都作为具有指定事件的时间值关联以存储在存储器中。 计数是在连接到振荡器的分频电路提供的逐渐变慢的频率范围内自动产生的。 该电路具有两种工作模式，一种累积模式和一种增量模式。 在累积模式下，计数开始于指定事件的第一次出现，并在获取停止时结束。 在增量模式下，控制可编程逻辑阵列在每次存储指定事件时自动将格雷码计数从而将时钟频率重置为最高频率。 因此，在每对事件之间开始时，分辨率或计数之间的时间是相同的。

公开(公告)号：US4697138A

公开(公告)日：1987-09-29

申请号：US875817

申请日：1986-06-18

Applicant: Mitsuhiro Morishita ,  Masayasu Sugimori

Inventor： Mitsuhiro Morishita ,  Masayasu Sugimori

IPC: G06F11/22 ,  G01R13/28 ,  G01R13/34 ,  G01R31/3177 ,  G06F11/25 ,  G01R15/00 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R13/34 ,  G06F11/25

Abstract: A logic analyzer includes a plurality of data sampling channels which are operative in response to respective different clock signals independent of one another. Information of the sequence in time in which the sampled data are produced in the plurality of the sampling channels is stored in a memory for the purpose of display. To this end, each of the sampling channels is provided with a clock discriminating circuit having two inputs supplied with a common clock signal generated internally and a clock signal specific to the associated sampling channel. The outputs of all the clock discriminating circuits are stored in a memory whose contents thus indicate the sequence in time in which the data are sampled in the plurality of the sampling channels.

Abstract translation: 逻辑分析器包括多个数据采样通道，其响应于彼此独立的各个不同的时钟信号而工作。 在多个采样通道中产生采样数据的时间序列的信息被存储在用于显示的目的的存储器中。 为此，每个采样通道设置有具有两个输入的时钟识别电路，该两个输入端被提供有内部产生的公共时钟信号以及特定于相关采样通道的时钟信号。 所有时钟识别电路的输出被存储在存储器中，其内容因此表示在多个采样通道中数据被采样的时间的顺序。

公开(公告)号：US4696004A

公开(公告)日：1987-09-22

申请号：US737466

申请日：1985-05-24

Applicant: Takayuki Nakajima ,  Tetsuo Aoki ,  Katsumi Kobayashi ,  Noboru Akiyama

Inventor： Takayuki Nakajima ,  Tetsuo Aoki ,  Katsumi Kobayashi ,  Noboru Akiyama

IPC: G01R31/3177 ,  G06F11/25 ,  G06F11/00

CPC classification number: G06F11/25 ,  G01R31/3177

Abstract: Logic output data of a plurality of channels simultaneously obtained from a circuit under test are sequentially input in a memory, and after inputting a predetermined amount of such data, they are compared with corresponding expected values. The input data are divided into blocks, each including a plurality of data. Whether a mismatch is present in the comparison results for each block is indicated by a respective block element, and such block elements are displayed in a predetermined arrangement. It is also possible to provide a conventional list display including the input timing corresponding to the comparison results in which a mismatch is present.

Abstract translation: 将从被测电路同时获得的多个通道的逻辑输出数据依次输入到存储器中，并且在输入预定量的这样的数据之后，将它们与相应的预期值进行比较。 输入数据被分成块，每个块包括多个数据。 每个块的比较结果中是否存在不匹配由相应的块元素指示，并且这些块元素以预定的布置显示。 还可以提供包括与存在不匹配的比较结果相对应的输入定时的常规列表显示。

公开(公告)号：US4673931A

公开(公告)日：1987-06-16

申请号：US713137

申请日：1985-03-18

Applicant: Howard G. Cunningham, Jr.

Inventor： Howard G. Cunningham, Jr.

IPC: G01R13/20 ,  G01R13/22 ,  G01R13/28 ,  G01R31/3177 ,  G06F11/25 ,  G09G5/36 ,  G09G1/16

CPC classification number: G01R13/22 ,  G01R31/3177 ,  G06F11/25

Abstract: Acquired sampled waveform data is displayed on a screen as a busform, wherein a change of state in the waveform during a sampling interval is represented by a solid block character on the screen, and wherein the lack of a change of state in any of the channels during a sampling interval is represented by a space character of the same width as the block character. The blocks and spaces representing contiguous sampling intervals are of the same width and are displayed in horizontal sequence across the screen such that the time between state changes is graphically represented by the horizontal distance between the blocks. Numbers indicating the associated waveform state are displayed when possible in the space or spaces following each block character.

Abstract translation: 获取的采样波形数据作为总线形式显示在屏幕上，其中在采样间隔期间波形状态的改变由屏幕上的实体块字符表示，并且其中在任何通道中缺少状态改变 在采样间隔期间由与块字符宽度相同的空格字符表示。 表示相邻采样间隔的块和间隔具有相同的宽度，并且以水平顺序显示在屏幕上，使得状态改变之间的时间由块之间的水平距离图形地表示。 指示相关波形状态的数字可能在每个块字符后面的空格或空格中显示。

公开(公告)号：US4623984A

公开(公告)日：1986-11-18

申请号：US763325

申请日：1985-08-07

Applicant: Hidemi Yokokawa ,  Rikichi Murooka ,  Miyuki Fukuzawa ,  Machiko Tomioka

Inventor： Hidemi Yokokawa ,  Rikichi Murooka ,  Miyuki Fukuzawa ,  Machiko Tomioka

IPC: G01R31/3177 ,  G06F11/25 ,  G06F3/153

CPC classification number: G01R31/3177 ,  G06F11/25

Abstract: A logic analyzer is disclosed which displays at least an input logic signal on a cathode ray tube, controls a cursor position on the cathode ray tube and obtains a relationship between a predetermined phenomenon included in the input logic signal and the cursor position. In a search mode, the predetermined phenomenon is a search word or a glitch. In a compare mode, the predetermined phenomenon is a reference logic signal.

Abstract translation: 公开了一种逻辑分析仪，其在阴极射线管上至少显示输入逻辑信号，控制阴极射线管上的光标位置，并获得输入逻辑信号中包含的预定现象与光标位置之间的关系。 在搜索模式中，预定的现象是搜索词或毛刺。 在比较模式中，预定现象是参考逻辑信号。

公开(公告)号：US4611281A

公开(公告)日：1986-09-09

申请号：US611839

申请日：1984-05-18

Applicant: Shouichi Suko ,  Hirohisa Hoshino

Inventor： Shouichi Suko ,  Hirohisa Hoshino

IPC: G06F9/22 ,  G01R13/28 ,  G06F11/22 ,  G06F11/25 ,  G06F11/00

CPC classification number: G06F11/25

Abstract: The apparatus for analyzing the operation of a microprocessor provides a switch for instructing the commencement of a data search and a switch for specifying an internal register of the microprocessor, and when a data search is commenced, searches for and displays the data when an instruction is executed by which the contents of the specified internal register is changed.

Abstract translation: 用于分析微处理器的操作的装置提供用于指示开始数据搜索的开关和用于指定微处理器的内部寄存器的开关，并且当数据搜索开始时，当指令是 执行指定的内部寄存器的内容被改变。