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公开(公告)号：US09916805B2
公开(公告)日：2018-03-13
申请号：US14913991
申请日：2016-01-28
Inventor： Yafeng Li , Jinfang Wu
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2092 , G09G3/3696 , G09G2300/0408 , G09G2310/0267 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/08 , G09G2320/0214 , G11C19/184 , G11C19/28
Abstract: The invention provides a GOA circuit for LTPS-TFT, by adding the twelfth and thirteenth TFTs (T12, T13) controlled by output ends (G(n−1), G(n+1)) of (n−1)-th and (n+1)-th GOA units, the drain of twelfth TFT T12 connected through the fourth node (W1(n)) to source of first TFT (T1), the drain of first TFT (T1) connected to output end of (n−1)-th GOA unit, the drain of thirteenth TFT (T13) connected through the fifth node W2(n) to source of third TFT (T3), the drain of third TFT (T3) connected to output end of (n+1)-th GOA unit; the first and third TFTs (T1, T3) controlled respectively by the forward and backward scan DC control signals (U2D, D2U) to reduce leakage of twelfth TFT (T12) in forward scanning and leakage of thirteenth TFT (T13) in backward scanning. As such, the leakage in key TFTs is reduced and GOA circuit stability is improved.
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公开(公告)号：US09905493B2
公开(公告)日：2018-02-27
申请号：US14914655
申请日：2016-01-28
Inventor： Yafeng Li , Xiangyi Peng
IPC: G02F1/133 , H01L23/34 , H01L27/12 , H01L29/786 , G02F1/1362 , G02F1/1368 , G02F1/1333
CPC classification number: H01L23/345 , G02F1/133382 , G02F1/136209 , G02F1/1368 , G02F2202/104 , H01L27/1222 , H01L27/124 , H01L27/1255 , H01L29/78633 , H01L29/78672
Abstract: The invention provides an array substrate and activation method for TFT elements in the array substrate. The array substrate comprises a shielding metal layer (10) and a TFT layer (20) disposed on the shielding metal layer (10); by connecting the shielding metal blocks (11) on the shielding metal layer (10) to electricity to heat up the shielding metal blocks (11) for pre-heating the TFT layer (20) to accelerate activating the TFT elements in the TFT layer (20). The activation method, by connecting the shielding metal blocks (11) on the shielding metal layer (10) to electricity to heat up the shielding metal blocks (11) for pre-heating the TFT layer (20) before activating the TFT elements in the TFT layer (20), accelerates activating the TFT elements in the TFT layer (20). The method is applicable to activating the TFT elements in array substrate in low temperature environment.
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公开(公告)号：US20180031877A1
公开(公告)日：2018-02-01
申请号：US14914653
申请日：2016-01-29
Inventor： Yafeng Li
IPC: G02F1/1335 , G03F7/00 , G09G3/36 , G02F1/1368
CPC classification number: G02F1/136209 , G02F1/1335 , G02F1/133512 , G02F1/133514 , G02F1/133621 , G02F1/13394 , G02F1/1343 , G02F1/1362 , G02F1/1368 , G02F2001/133567 , G02F2001/136218 , G02F2001/136222 , G03F7/0007 , G09G3/36
Abstract: The invention provides an LCD, wherein the color-resist layer, photo-spacer and TFT layer are disposed at the same second substrate of LC panel to achieve higher alignment precision by reducing offset between layers of second substrate; also, because the backlight module is disposed at the side near first substrate of LC panel and second substrate uses a top gate structure, when the backlight module light enters from first substrate side of LC panel, the gate shields the channel region of polysilicon layer to improve current leakage of second substrate; moreover, the shielding metal layer at the bottom of the second substrate side is made of a black metal, the shielding metal layer at the bottom can prevent reflection of light from second substrate side caused by metal to reduce contrast. As such, the present invention has a simple structure, and saves black matrix fabrication compared to conventional technology.
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公开(公告)号：US09792871B2
公开(公告)日：2017-10-17
申请号：US14905967
申请日：2015-12-23
IPC: G09G3/36 , G02F1/1345 , G02F1/1368
CPC classification number: G09G3/3677 , G02F1/13454 , G02F1/1368 , G09G2300/0819 , G09G2310/0251 , G09G2310/0286 , G09G2310/08 , G09G2330/021
Abstract: A GOA circuit includes GOA circuit units. When scan signal outputted by a previous stage GOA circuit unit and a next stage GOA circuit unit are at a low level, a fifth transistor controlled by the scan signal of previous stage GOA circuit unit and a sixth transistor controlled by the scan signal of a next stage GOA circuit unit turn on, so that the current stage GOA circuit unit starts to operate, and voltage of a control node becomes the same as the first constant voltage. When a third clock signal is triggered, the scan signal of the previous stage GOA circuit unit is charged from the low level, which was maintained previously, to the first constant voltage. Therefore, scan signal of GOA circuit unit will not affect the normal stage transmission of other GOA circuit units, and mitigate the problem of outputting redundant scan signal pulse.
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公开(公告)号：US09779684B2
公开(公告)日：2017-10-03
申请号：US14906702
申请日：2015-12-22
Inventor： Yafeng Li
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3648 , G09G3/3696 , G09G2230/00 , G09G2300/0408 , G09G2300/0809 , G09G2310/0286 , G11C19/28
Abstract: A GOA circuit includes GOA circuit units coupled in series. Each GOA circuit unit includes an input control module, an output control module, a pull-down module, and a pull-up holding module. The input control module includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Each GOA circuit unit includes ten transistors. Because the GOA circuit unit proposed by the present invention comprises fewer transistors, it is good for being used in displays with a narrow bezel. In addition, the GOA circuit unit comprises an input control module comprising a second transistor and a third transistor controlled by a first gate turn-on signal. A first transistor and the second transistor are connected in series, and the third transistor and a fourth transistor are connected in series, which reduces leakage current. It provides a beneficiary effect that the stability of the GOA circuit unit is improved.
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Patent Agency Ranking
公开(公告)号：US11741872B2
公开(公告)日：2023-08-29
申请号：US17046835
申请日：2020-06-23
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2300/0408 , G09G2300/0426 , G09G2310/0267 , G09G2310/08
Abstract: A GOA circuit and a display panel are provided. The GOA circuit includes a first pull-down module for pulling down a voltage level of a current-stage gate driving signal, a second pull-down module for pulling down a voltage level of the first node, a third pull-down module for pulling down a voltage level of the second node, and a fourth pull-down module for pulling down the voltage level of the current-stage gate driving signal. The GOA circuit raises the effect of pulling down the current-stage gate driving signal.
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公开(公告)号：US11315512B2
公开(公告)日：2022-04-26
申请号：US16652167
申请日：2020-03-24
Abstract: A gate driver on array (GOA) circuit is provided. The GOA circuit includes a plurality of cascading GOA units. One of the GOA unit includes: a scan control module, an anti-backfill module connected to a constant high-level signal and the scan control module, a cascading reset module, and a gate signal output module. Base on functions of prior art solution, the provided GOA circuit of the disclosure reduces two types of signal to simplify signal traces at the bezel to realize a narrow bezel design.
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公开(公告)号：US11275282B2
公开(公告)日：2022-03-15
申请号：US16764419
申请日：2020-01-09
IPC: G02F1/1362 , G02F1/1335 , G02F1/1343 , G09G3/36 , G02F1/133 , G02F1/1333 , G09G3/00 , G02F1/1345
Abstract: The present application provides a liquid crystal display panel and a display device. Invalid pixels of the liquid crystal display panel include a test pixel. In this structure, when no tests are required, the test pixel is in an off state, and there is no voltage difference between a pixel electrode and a common electrode to cause rotation of liquid crystals. When a test is required, the test pixel is in an on state, and the pixel electrode is disconnected from the common electrode to cause a voltage difference, so that the liquid crystals are normally rotated.
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公开(公告)号：US20210407451A1
公开(公告)日：2021-12-30
申请号：US16652167
申请日：2020-03-24
IPC: G09G3/36
Abstract: A gate driver on array (GOA) circuit is provided. The GOA circuit includes a plurality of cascading GOA units. One of the GOA unit includes: a scan control module, an anti-backfill module connected to a constant high-level signal and the scan control module, a cascading reset module, and a gate signal output module. Base on functions of prior art solution, the provided GOA circuit of the disclosure reduces two types of signal to simplify signal traces at the bezel to realize a narrow bezel design.
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公开(公告)号：US20200320949A1
公开(公告)日：2020-10-08
申请号：US16308813
申请日：2018-09-27
Inventor： Yafeng Li , Jinfang Wu
IPC: G09G3/36
Abstract: The invention provides a GOA circuit. The first node control module of the GOA circuit provided by the invention comprises a tenth TFT, an eleventh TFT and a twelfth TFT of N-type TFTs, when the voltage of the first node is high, the gate-to-source voltage difference of the twelfth TFT is the threshold voltage thereof, so that the drain-source voltage difference of the eleventh TFT is also the threshold voltage of the twelfth TFT, thereby making the resistance between the drain of the tenth TFT and the first node is extremely large, which can avoid the impact of leakage current generated by the tenth TFT on the voltage of the first node when the noise and coupling in the second node occurs, and to ensure the normal output of the scan signal.
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