公开(公告)号：US12027572B2

公开(公告)日：2024-07-02

申请号：US17491451

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/64 ,  H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L28/10 ,  H01L23/645 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48177 ,  H01L2924/1425

Abstract: In a described example, an apparatus includes a transformer including: an isolation dielectric layer with a first surface and a second surface opposite the first surface; a first inductor formed over the first surface, the first inductor comprising a first layer of ferrite material, and a first coil at least partially covered by the first layer of ferrite material; and a second inductor formed over the second surface, the second inductor comprising a second layer of ferrite material and a second coil at least partially covered by the second layer of ferrite material.

公开(公告)号：US11881461B2

公开(公告)日：2024-01-23

申请号：US17491522

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/60 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647

Abstract: In a described example, an apparatus includes: a semiconductor die having bond pads on a device side surface, the semiconductor die having a ground plane spaced from the bond pads by a spacing distance. The bond pads have an upper surface for receiving a ball bond, and an outer boundary, the bond pads having vertical sides extending from the upper surface to a bottom surface, the bottom surface formed over the device side surface of the semiconductor die. A protective overcoat (PO) is formed overlying the ground plane and overlying the vertical sides of the bond pads, and overlying a portion of the upper surface of the bond pads, and having an opening exposing the remaining portion of the upper surface of the bond pads, the protective overcoat having a dielectric constant of less than 3.8.

公开(公告)号：US20230245957A1

公开(公告)日：2023-08-03

申请号：US18295793

申请日：2023-04-04

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  G01R19/00 ,  G01R15/20 ,  H10N52/00

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L24/05 ,  H01L21/4803 ,  H01L24/85 ,  H01L21/56 ,  G01R19/0092 ,  G01R15/202 ,  H10N52/101 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/48175

Abstract: In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.

公开(公告)号：US11594474B2

公开(公告)日：2023-02-28

申请号：US17246568

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Enis Tuncer

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

公开(公告)号：US20220384370A1

公开(公告)日：2022-12-01

申请号：US17330621

申请日：2021-05-26

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/495 ,  H01L49/02 ,  H01L21/48 ,  H01L21/56

Abstract: An electronic device includes a magnetic assembly with a multilevel lamination or metallization structure having a core layer, dielectric layers and conductive features formed in metal layers on or between the dielectric layers in respective planes of orthogonal first and second directions and stacked along an orthogonal third direction. The conductive features include first and second patterned conductive features forming first and second windings, first and second conductive capacitor plates, and first and second conductive field plates, in which the first conductive capacitor plate is between the first conductive field plate and the core layer along the third direction and the second conductive capacitor plate is between the second conductive field plate and the core layer along the third direction.

公开(公告)号：US20210305024A1

公开(公告)日：2021-09-30

申请号：US16828869

申请日：2020-03-24

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  John Paul Tellkamp

IPC: H01J37/32 ,  H01L21/02

Abstract: In a described example, a method includes loading at least one package substrate strip including electronic device dies mounted on the at least one package substrate strip into a plasma process chamber; positioning at least one E-field shield in the plasma process chamber spaced from and over the at least one package substrate strip; and plasma cleaning the at least one package substrate strip.

公开(公告)号：US20210210462A1

公开(公告)日：2021-07-08

申请号：US16734836

申请日：2020-01-06

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Enis Tuncer ,  Christopher Daniel Manack ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor surface having circuitry with metal interconnect layers over the semiconductor surface including a selected metal interconnect layer providing an interconnect trace having a first and second end. A top dielectric layer is on the top metal interconnect layer. A redistribution layer (RDL) is on the top dielectric layer. A corrosion interruption structure (CIS) including the interconnect trace bridges an interrupting gap in a trace of the RDL.

公开(公告)号：US20210175326A1

公开(公告)日：2021-06-10

申请号：US17017642

申请日：2020-09-10

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Enis Tuncer ,  Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L29/06 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: In described examples of an isolation device, an isolation die that has a set of bond pads is mounted on a first lead frame that has a set of leads. A portion of the bond pads are coupled to respective leads. A first mold material encapsulates the isolation device and the first lead frame forming a first package. The first package is mounted on a second lead frame that has a set of leads. A portion of the first lead frame leads is coupled to respective ones of the second lead frame leads. A second mold material encapsulates the first package and the second lead frame.

公开(公告)号：US10892405B2

公开(公告)日：2021-01-12

申请号：US16404978

申请日：2019-05-07

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G01R15/20 ,  H01L23/495 ,  G01R33/07 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US10883953B2

公开(公告)日：2021-01-05

申请号：US16162011

申请日：2018-10-16

Applicant: Texas Instruments Incorporated

Inventor： Enis Tuncer ,  Vikas Gupta

IPC: G01N27/22 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00

Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.