DATA STORAGE SYSTEM DIE SET MAPPING
    41.
    发明申请

    公开(公告)号:US20200004448A1

    公开(公告)日:2020-01-02

    申请号:US16021134

    申请日:2018-06-28

    Abstract: A data storage system can arrange semiconductor memory into a plurality of die sets that each store a top-level map with each top-level map logging information about user-generated data stored in a die set in which the top-level map is stored. A journal can be stored in at least one die set of the plurality of die sets with each journal logging a change to user-generated data stored in the die set of the plurality of die sets in which the journal and top-level map are each located.

    Encryption key shredding to protect non-persistent data

    公开(公告)号:US10142304B2

    公开(公告)日:2018-11-27

    申请号:US15245051

    申请日:2016-08-23

    Abstract: Systems and methods for encryption key shredding to protect non-persistent data are described. In one embodiment, the storage system device may include a storage drive and a controller. In some embodiments, the controller may be configured to power on the storage drive, identify an encryption key on the storage drive created upon powering on the storage drive, and encrypt data in a cache of the storage drive using the encryption key. In some embodiments, the controller may be configured to power off the storage drive and delete the encryption key upon powering off the storage drive. In some cases, the storage drive may include at least one of a solid state drive and a hard disk drive. In some embodiments, the storage drive may include a hybrid storage drive that includes both a solid state drive and a hard disk drive.

    Background reads to condition programmed semiconductor memory cells

    公开(公告)号:US10095568B2

    公开(公告)日:2018-10-09

    申请号:US15498595

    申请日:2017-04-27

    Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

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