公开(公告)号：US20210226011A1

公开(公告)日：2021-07-22

申请号：US16928508

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Yeonchoo CHO ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

公开(公告)号：US20210159183A1

公开(公告)日：2021-05-27

申请号：US17165246

申请日：2021-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun BYUN ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20200035611A1

公开(公告)日：2020-01-30

申请号：US16215899

申请日：2018-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Byun ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20160351491A1

公开(公告)日：2016-12-01

申请号：US15052290

申请日：2016-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Seongjun PARK ,  Hyunjae SONG ,  Hyangsook LEE ,  Yeonchoo CHO

IPC: H01L23/528 ,  H01L27/06 ,  H01L23/532

CPC classification number: H01L27/0629 ,  H01L23/53271 ,  H01L27/101 ,  H01L27/228

Abstract: A wiring structure may include at least two conductive material layers and a two-dimensional layered material layer in an interface between the at least two conductive material layers. The two-dimensional layered material layer may include a grain expander layer which causes grain size of a conductive material layer which is on the two-dimensional layered material layer to be increased. Increased grain size may result in resistance of the second conductive material layer to be reduced. As a result, the total resistance of the wiring structure may be reduced. The two-dimensional layered material layer may contribute to reducing a total thickness of the wiring structure. Thus, a low-resistance and high-performance wiring structure without an increase in a thickness thereof may be implemented.

Abstract translation: 布线结构可以包括在至少两个导电材料层之间的界面中的至少两个导电材料层和二维层状材料层。 二维层状材料层可以包括使二维层状材料层上的导电性材料层的粒径增大的晶粒扩展层。 增加的晶粒尺寸可能导致第二导电材料层的电阻降低。 结果，可以减小布线结构的总电阻。 二维层状材料层可有助于减小布线结构的总厚度。 因此，可以实现不增加其厚度的低电阻和高性能布线结构。