公开(公告)号：US20220197741A1

公开(公告)日：2022-06-23

申请号：US17207600

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rekha PITCHUMANI ,  Zongwang LI

IPC: G06F11/10 ,  G06F11/14 ,  G06F11/07

Abstract: A storage device is disclosed. The storage device may include storage for data. A controller may manage writing the data to the storage and reading the data from the reading storage. A data quality metric table may map a first number of errors to a first data quality metric and map a second number of errors to a second data quality metric. A transmitter may return the data quality metric table to a host.

公开(公告)号：US20220164138A1

公开(公告)日：2022-05-26

申请号：US17117008

申请日：2020-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing YANG ,  Jingpei YANG ,  Rekha PITCHUMANI

IPC: G06F3/06

Abstract: A multi-stream memory system includes an in-device data processor including a first data processing engine and a second data processing engine, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform: identifying a stream ID of an input stream, identifying the first data processing engine as being associated with the stream ID based on a stream assignment table, and applying the first data processing engine to the input stream to generate processed data.

公开(公告)号：US20220121363A1

公开(公告)日：2022-04-21

申请号：US17563019

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F3/06 ,  G06F11/14 ,  G06F11/20

Abstract: A method for storing data may include receiving user data at a group of storage devices, wherein the storage devices are interconnected, erasure coding the user data into redundancy blocks at the group of storage devices, and storing the redundancy blocks on at least two of the storage devices. The erasure encoding may be distributed among at least two of the storage devices. The redundancy blocks may be arranged in reliability groups. The redundancy blocks may be grouped by the storage devices independently of the partitioning of the user data by the user. The method may further include recovering data based on redundancy blocks. A storage device may include a storage medium, a network interface configured to communicate with one or more other storage devices, and a storage processing unit configured to erasure code user data into redundancy blocks cooperatively with the one or more other storage devices.

公开(公告)号：US20220113915A1

公开(公告)日：2022-04-14

申请号：US17497882

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Seok KI ,  Krishna T. MALLADI ,  Rekha PITCHUMANI

IPC: G06F3/06

Abstract: A device may include an interconnect interface, a memory system including one or more first type memory devices to receive first data, one or more second type memory devices to receive second data, and an accelerator configured to perform an operation using the first data and the second data. The memory system may further include a cache configured to cache the second data for the one or more second type memory devices. A device may include an interconnect interface, a memory system coupled to the interconnect interface to receive data, an accelerator coupled to the memory system, and virtualization logic configured to partition one or more resources of the accelerator into one or more virtual accelerators, wherein a first one of the one or more virtual accelerators may he configured to perform a first operation on a first portion of the data.

公开(公告)号：US20210334162A1

公开(公告)日：2021-10-28

申请号：US17367315

申请日：2021-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mian QIN ,  Joo Hwan LEE ,  Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F11/10 ,  G06F13/28

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

公开(公告)号：US20210232310A1

公开(公告)日：2021-07-29

申请号：US15930422

申请日：2020-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rekha PITCHUMANI ,  Yang Seok KI

IPC: G06F3/06 ,  G06F11/20 ,  G06F11/14

Abstract: A method for storing data may include receiving user data at a group of storage devices, wherein the storage devices are interconnected, erasure coding the user data into redundancy blocks at the group of storage devices, and storing the redundancy blocks on at least two of the storage devices. The erasure encoding may be distributed among at least two of the storage devices. The redundancy blocks may be arranged in reliability groups. The redundancy blocks may be grouped by the storage devices independently of the partitioning of the user data by the user. The method may further include recovering data based on redundancy blocks. A storage device may include a storage medium, a network interface configured to communicate with one or more other storage devices, and a storage processing unit configured to erasure code user data into redundancy blocks cooperatively with the one or more other storage devices.

公开(公告)号：US20240361952A1

公开(公告)日：2024-10-31

申请号：US18427816

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rekha PITCHUMANI ,  Yang Seok KI ,  Zongwang LI ,  Marie Mai NGUYEN ,  Tong ZHANG

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A device may include cache media, storage media, a communication interface configured to communicate with the cache media and the storage media, and at least one control circuit to configure a portion of the storage media as visible memory, and configure a portion of the cache media as a cache for the portion of the storage media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media to persist the portion of the cache media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media as visible storage.

公开(公告)号：US20240330193A1

公开(公告)日：2024-10-03

申请号：US18226759

申请日：2023-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Susav Lal SHRESTHA ,  Zongwang LI ,  Rekha PITCHUMANI

IPC: G06F12/0891 ,  G06F16/903 ,  G06F16/93

CPC classification number: G06F12/0891 ,  G06F16/90335 ,  G06F16/93 ,  G06F2212/1041 ,  G06F2212/163

Abstract: A system is disclosed. A processor may include a local memory. A memory may be connected to the processor. A cache-coherent interconnect storage device may also be connected to the processor. An embedded management unit (EMU) may be configured to manage the storage of a document embedding vector in the local memory, the memory, or the cache-coherent interconnect storage device.

公开(公告)号：US20240303196A1

公开(公告)日：2024-09-12

申请号：US18238312

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Ho Bin LEE ,  Rekha PITCHUMANI

IPC: G06F12/0862 ,  G06F12/123

CPC classification number: G06F12/0862 ,  G06F12/123

Abstract: There is provided a memory controller including an interface and a processor. The processor fetches a memory request in one of a plurality of queues storing a plurality of memory requests from a host, compares a destination address of the memory request with a first stored destination address, among one or more stored destination addresses in a storage, associates the memory request with the first stored destination address in the storage based on a match between the destination address of the memory request and the first stored destination address in the storage, and processes one or more entries in the storage in response to the memory request.

公开(公告)号：US20240201909A1

公开(公告)日：2024-06-20

申请号：US18587929

申请日：2024-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang Seok KI ,  Krishna T. MALLADI ,  Rekha PITCHUMANI

IPC: G06F3/06

CPC classification number: G06F3/0664 ,  G06F3/0604 ,  G06F3/0679

Abstract: A device may include an interconnect interface, a memory system including one or more first type memory devices to receive first data, one or more second type memory devices to receive second data, and an accelerator configured to perform an operation using the first data and the second data. The memory system may further include a cache configured to cache the second data for the one or more second type memory devices. A device may include an interconnect interface, a memory system coupled to the interconnect interface to receive data, an accelerator coupled to the memory system, and virtualization logic configured to partition one or more resources of the accelerator into one or more virtual accelerators, wherein a first one of the one or more virtual accelerators may be configured to perform a first operation on a first portion of the data.