SYSTEM, DEVICE AND METHOD FOR STORAGE DEVICE ASSISTED LOW-BANDWIDTH DATA REPAIR

    公开(公告)号:US20230016236A1

    公开(公告)日:2023-01-19

    申请号:US17948216

    申请日:2022-09-19

    Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

    AUTOMATIC DATA SEPARATION AND PLACEMENT FOR COMPRESSED DATA IN A STORAGE DEVICE

    公开(公告)号:US20220413707A1

    公开(公告)日:2022-12-29

    申请号:US17898474

    申请日:2022-08-29

    Abstract: A storage device is disclosed. The storage device may include storage for data. A host interface logic may receive a dataset and a logical address from a host. A stream assignment logic may assign a stream identifier (ID) to a compressed dataset based on a compression characteristic of the compressed dataset. The stream ID may be one of at least two stream IDs; the compressed dataset may be determined based on the dataset. A logical-to-physical translation layer may map the logical address to a physical address in the storage. A controller may store the compressed dataset at the physical address using the stream ID.

    SYSTEM AND METHOD FOR IN-SSD DATA PROCESSING ENGINE SELECTION BASED ON STREAM IDS

    公开(公告)号:US20220164138A1

    公开(公告)日:2022-05-26

    申请号:US17117008

    申请日:2020-12-09

    Abstract: A multi-stream memory system includes an in-device data processor including a first data processing engine and a second data processing engine, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform: identifying a stream ID of an input stream, identifying the first data processing engine as being associated with the stream ID based on a stream assignment table, and applying the first data processing engine to the input stream to generate processed data.

    OFFLOADED DEVICE-DRIVEN ERASURE CODING

    公开(公告)号:US20220121363A1

    公开(公告)日:2022-04-21

    申请号:US17563019

    申请日:2021-12-27

    Abstract: A method for storing data may include receiving user data at a group of storage devices, wherein the storage devices are interconnected, erasure coding the user data into redundancy blocks at the group of storage devices, and storing the redundancy blocks on at least two of the storage devices. The erasure encoding may be distributed among at least two of the storage devices. The redundancy blocks may be arranged in reliability groups. The redundancy blocks may be grouped by the storage devices independently of the partitioning of the user data by the user. The method may further include recovering data based on redundancy blocks. A storage device may include a storage medium, a network interface configured to communicate with one or more other storage devices, and a storage processing unit configured to erasure code user data into redundancy blocks cooperatively with the one or more other storage devices.

    SYSTEMS, METHODS, AND DEVICES FOR ACCELERATORS WITH VIRTUALIZATION AND TIERED MEMORY

    公开(公告)号:US20220113915A1

    公开(公告)日:2022-04-14

    申请号:US17497882

    申请日:2021-10-08

    Abstract: A device may include an interconnect interface, a memory system including one or more first type memory devices to receive first data, one or more second type memory devices to receive second data, and an accelerator configured to perform an operation using the first data and the second data. The memory system may further include a cache configured to cache the second data for the one or more second type memory devices. A device may include an interconnect interface, a memory system coupled to the interconnect interface to receive data, an accelerator coupled to the memory system, and virtualization logic configured to partition one or more resources of the accelerator into one or more virtual accelerators, wherein a first one of the one or more virtual accelerators may he configured to perform a first operation on a first portion of the data.

    FPGA ACCELERATION SYSTEM FOR MSR CODES

    公开(公告)号:US20210334162A1

    公开(公告)日:2021-10-28

    申请号:US17367315

    申请日:2021-07-02

    Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

    OFFLOADED DEVICE-DRIVEN ERASURE CODING

    公开(公告)号:US20210232310A1

    公开(公告)日:2021-07-29

    申请号:US15930422

    申请日:2020-05-12

    Abstract: A method for storing data may include receiving user data at a group of storage devices, wherein the storage devices are interconnected, erasure coding the user data into redundancy blocks at the group of storage devices, and storing the redundancy blocks on at least two of the storage devices. The erasure encoding may be distributed among at least two of the storage devices. The redundancy blocks may be arranged in reliability groups. The redundancy blocks may be grouped by the storage devices independently of the partitioning of the user data by the user. The method may further include recovering data based on redundancy blocks. A storage device may include a storage medium, a network interface configured to communicate with one or more other storage devices, and a storage processing unit configured to erasure code user data into redundancy blocks cooperatively with the one or more other storage devices.

    STORAGE DEVICE CACHE SYSTEM WITH MACHINE LEARNING

    公开(公告)号:US20250165405A1

    公开(公告)日:2025-05-22

    申请号:US18778907

    申请日:2024-07-19

    Abstract: A storage device is disclosed. An interface may receive a write request from an application to store a data. A first storage device may act as a cache. The first storage device may include a first storage unit associated with a first lifetime data. A second storage device may act as a persistent storage. The second storage device may include a second storage unit associated with a first placement data. The first storage device may be configured to store the data in the first storage unit associated with the first lifetime data based on a second lifetime data. The second storage device may be configured to store the data in the second storage unit associated with the first placement data based at least in part on the second lifetime data.

    SYSTEMS, METHODS, AND APPARATUS FOR DEVICES WITH MEMORY AND STORAGE CONFIGURATIONS

    公开(公告)号:US20240361952A1

    公开(公告)日:2024-10-31

    申请号:US18427816

    申请日:2024-01-30

    CPC classification number: G06F3/0656 G06F3/0604 G06F3/0679

    Abstract: A device may include cache media, storage media, a communication interface configured to communicate with the cache media and the storage media, and at least one control circuit to configure a portion of the storage media as visible memory, and configure a portion of the cache media as a cache for the portion of the storage media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media to persist the portion of the cache media. The portion of the storage media may be a first portion of the storage media, and the at least one control circuit may be to configure a second portion of the storage media as visible storage.

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