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公开(公告)号：US09634669B2
公开(公告)日：2017-04-25
申请号：US14971150
申请日：2015-12-16
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Salvatore Marco Rosselli , Daniele Mangano , Riccardo Condorelli
IPC: H03K19/177 , G06F15/78 , H03K19/00
CPC classification number: H03K19/0008 , G06F15/7867 , G06F2209/507 , H03K19/1737 , H03K19/1776
Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.
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42.发明授权公开(公告)号：US09632793B2
公开(公告)日：2017-04-25
申请号：US13888062
申请日：2013-05-06
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano
CPC classification number: G06F9/3867 , G06F9/3861 , G06F9/466 , G06F9/485 , G06F11/0766 , G06F11/0793 , G06F13/1605
Abstract: Current tasks being executed in a set of modules of a signal processing system managed via an interface block are aborted so as to permit the execution of new tasks by pipelining eliminating transactions of said current tasks and executing transactions of the new tasks. Upon arrival of a signal to abort the current tasks, data and/or memory accesses present in said interface block are discarded.
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公开(公告)号：US09389979B2
公开(公告)日：2016-07-12
申请号：US14038501
申请日：2013-09-26
Inventor： Daniele Mangano , Ignazio Antonino Urzi
CPC classification number: G06F11/27 , G06F11/2236 , G06F11/3648
Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.
Abstract translation: 系统包括处理器和通过互连网络连接的多个电路，其中与每个电路相关联的是相应的通信接口，被配置为在相应电路和互连网络之间交换数据。 特别地，调试单元与每个通信接口相关联。 每个调试单元可配置为数据插入点，其中调试单元通过相应的通信接口将数据发送到互连网络，或者每个调试单元可配置为数据接收点，其中调试单元通过 来自互连网络的相应通信接口的装置。
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44.发明申请公开(公告)号：US20150370734A1
公开(公告)日：2015-12-24
申请号：US14841522
申请日：2015-08-31
Applicant: STMicroelectronics S.R.L.
Inventor： Daniele Mangano , Mirko Dondini , Salvatore Pisasale
CPC classification number: G06F13/28 , G06F3/0619 , G06F3/0655 , G06F3/067 , G06F13/4059 , G06F2213/0038
Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
Abstract translation: 通信接口将传输电路与互连网络耦合。 发送电路请求发送预定量的数据。 通信接口从发送电路接收数据段，将数据段存储在存储器中，并且验证存储器是否包含预定量的数据。 在存储器包含预定量的数据的情况下，通信接口开始存储在存储器中的数据的发送。 或者，在存储器包含小于预定数据量的数据量的情况下，通信接口确定从上述发送电路接收到从发送请求或第一基准开始经过的时间的参数， 并验证所经过的时间是否超过时间阈值。 在经过时间超过时间阈值的情况下，通信接口开始存储在存储器中的数据的发送。
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公开(公告)号：US20150207581A1
公开(公告)日：2015-07-23
申请号：US14604439
申请日：2015-01-23
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Salvatore Pisasale
CPC classification number: H04L43/0858 , G06F1/04 , G06F13/4291 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/10
Abstract: A communication system for interfacing a transmitting circuit with a receiving circuit includes a transmission interface for receiving data from the transmitting circuit and transmitting the data received over at least one data line in response to a transmission clock signal. The communication system also includes a reception interface configured for receiving the data in response to a reception clock signal and transmitting the data received to the receiving circuit. In particular, the system is configured for generating a plurality of clock signals that have the same frequency but are phase-shifted with respect to one another. In addition, during a calibration phase, the system is configured for selecting one of the clock signals for the transmission clock signal or reception clock signal via selecting at least one of the clock signals for transmission of test signals via the transmission interface and verifying whether the test signals received via the reception interface are correct. The system is further configured to use, during normal operation, the clock signal selected during the calibration phase for transmission of data.
Abstract translation: 用于将发射电路与接收电路接口的通信系统包括用于从发射电路接收数据的传输接口，并响应于传输时钟信号发射通过至少一条数据线接收的数据。 通信系统还包括：接收接口，被配置为响应于接收时钟信号接收数据，并将接收到的数据发送到接收电路。 特别地，该系统被配置为产生具有相同频率但是相对于彼此相移的多个时钟信号。 此外，在校准阶段期间，系统被配置为通过经由传输接口选择用于传输测试信号的时钟信号中的至少一个来选择传输时钟信号或接收时钟信号中的一个时钟信号，并且验证 通过接收接口接收到的测试信号是正确的。 该系统还被配置为在正常操作期间使用在校准阶段期间选择的用于传输数据的时钟信号。
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Patent Agency Ranking
公开(公告)号：US11543842B2
公开(公告)日：2023-01-03
申请号：US16803942
申请日：2020-02-27
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Mirko Dondini , Daniele Mangano , Riccardo Condorelli
IPC: G05F1/00 , G05F1/575 , G05B19/042 , G06F13/40 , H03B5/32 , H03K19/17736
Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.
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公开(公告)号：US10168443B2
公开(公告)日：2019-01-01
申请号：US14835935
申请日：2015-08-26
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Daniele Mangano , Riccardo Condorelli
Abstract: A system for interfacing an LC sensor includes a starter configured to selectively start an oscillation of the LC sensor. The system also includes an analog peak detector configured to determine a signal (Vpeak) being indicative of a peak voltage of the oscillation of the LC sensor and a detector configured to determine a state of the LC sensor as a function of the signal (Vpeak) determined by the analog peak detector.
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公开(公告)号：US09959226B2
公开(公告)日：2018-05-01
申请号：US14841522
申请日：2015-08-31
Applicant: STMicroelectronics S.R.L.
Inventor： Daniele Mangano , Mirko Dondini , Salvatore Pisasale
CPC classification number: G06F13/28 , G06F3/0619 , G06F3/0655 , G06F3/067 , G06F13/4059 , G06F2213/0038
Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
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公开(公告)号：US09823965B2
公开(公告)日：2017-11-21
申请号：US15080307
申请日：2016-03-24
Inventor： Daniele Mangano , Michele Alessandro Carrano , Gaetano Di Stefano , Antonin Fried
CPC classification number: G06F11/1068 , G06F11/1044 , G11C29/52
Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
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公开(公告)号：US20170187380A1
公开(公告)日：2017-06-29
申请号：US15458692
申请日：2017-03-14
Applicant: STMicroelectronics S.r.l.
Inventor： Salvatore Marco Rosselli , Daniele Mangano , Riccardo Condorelli
IPC: H03K19/00 , H03K19/173 , G06F15/78 , H03K19/177
CPC classification number: H03K19/0008 , G06F15/7867 , G06F2209/507 , H03K19/1737 , H03K19/1776
Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.
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