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    Apparatus and method for decoding ROI regions in image
    41.
    发明授权
    Apparatus and method for decoding ROI regions in image 有权

    公开(公告)号：US10771163B2

    公开(公告)日：2020-09-08

    申请号：US16163581

    申请日：2018-10-18

    Applicant: MEDIATEK INC.

    Inventor： Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

    IPC: H04B10/69 ,  H04N19/70 ,  H04N19/184 ,  G06T9/00 ,  H04N19/127 ,  H04N19/44 ,  H04N19/42 ,  H04N19/17

    Abstract: A decoding apparatus is used for decoding region of interest (ROI) regions in an image, and includes a storage device, a pre-processing circuit, a decoding circuit, and an information fetching circuit. The pre-processing circuit performs a syntax pre-parsing operation upon a bitstream to obtain necessary information of the ROI regions, and stores the necessary information into the storage device. The decoding circuit performs a decoding operation upon the bitstream to decode the ROI regions, wherein the decoding operation includes syntax parsing of the bitstream. The information fetching circuit reads and analyzes the necessary information, and delivers at least a portion of the necessary information to the decoding circuit. A processing time of obtaining necessary information of one ROI region at the pre-processing circuit overlaps a processing time of decoding another ROI region at the decoding circuit.

    METHOD AND APPARATUS FOR GENERATING MOTION FIELD MOTION VECTORS FOR BLOCKS OF CURRENT FRAME IN ON-THE-FLY MANNER
    42.
    发明申请
    METHOD AND APPARATUS FOR GENERATING MOTION FIELD MOTION VECTORS FOR BLOCKS OF CURRENT FRAME IN ON-THE-FLY MANNER 审中-公开

    公开(公告)号：US20200177909A1

    公开(公告)日：2020-06-04

    申请号：US16697119

    申请日：2019-11-26

    Applicant: MEDIATEK INC.

    Inventor： Yung-Chang Chang ,  Chia-Yun Cheng ,  Cheng-Han Li ,  Hong-Cheng Lin ,  Chi-Hung Chen

    IPC: H04N19/52 ,  H04N19/176 ,  H04N19/119

    Abstract: A motion vector (MV) projection method includes generating motion field motion vectors (MFMVs) for a first portion of a current frame by applying MV projection to MVs of a portion of each of reference frames and storing the MFMVs of the first portion of the current frame into an MFMV buffer, and generating MFMVs for a second portion of the current frame by applying MV projection to MVs of a portion of each of the reference frames and storing the MFMVs of the second portion of the current frame into the MFMV buffer. The second portion does not overlap the first portion. Before generating the MFMVs for the second portion of the current frame is done, at least one of the MFMVs of the first portion is read from the MFMV buffer and involved in motion vector determination of at least one coding block included in the first portion.

    High efficiency adaptive loop filter processing for video coding
    43.
    发明授权
    High efficiency adaptive loop filter processing for video coding 有权

    公开(公告)号：US10609417B2

    公开(公告)日：2020-03-31

    申请号：US15596752

    申请日：2017-05-16

    Applicant: MEDIATEK INC.

    Inventor： Ping Chao ,  Chih-Ming Wang ,  Yung-Chang Chang

    IPC: H04N19/82 ,  H04N19/42 ,  H04N19/423

    Abstract: A method and a circuit for adaptive loop filtering in a video coding system are described. The method can include receiving a block of samples generated from a previous-stage filter circuit in a filter pipeline, the block of samples being one of multiple blocks included in a current picture, performing, in parallel, adaptive loop filter (ALF) processing for multiple target samples in the block of samples, while the previous-stage filter circuit is simultaneously processing another block in the current picture, storing, in a buffer, first samples each having a filter input area defined by a filter shape that includes at least one sample which has not been received, and storing, in the buffer, second samples included in the filter input areas of the first samples.

    Residual processing circuit using single-path pipeline or multi-path pipeline and associated residual processing method
    45.
    发明授权
    Residual processing circuit using single-path pipeline or multi-path pipeline and associated residual processing method 有权

    公开(公告)号：US10244248B2

    公开(公告)日：2019-03-26

    申请号：US15438774

    申请日：2017-02-22

    Applicant: MEDIATEK INC.

    Inventor： Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

    IPC: H04N19/44 ,  H04N19/436 ,  H04N19/61

    Abstract: A residual processing circuit has a single-path pipeline and a single-path controller. The single-path pipeline has an inverse scan (IS) circuit, an inverse quantization (IQ) circuit and an inverse transform (IT) circuit arranged to process a current non-zero residual data block in a pipeline manner. The current non-zero residual data block is at least a portion of a transform unit. The single-path controller controls pipelined processing of the current non-zero residual data block at the single-path pipeline. The single-path controller instructs the IS circuit to start IS processing of a next non-zero residual data block before the IT circuit finishes a first half of IT processing of the current non-zero residual data block.

    Video transmitting system with on-the-fly encoding and on-the-fly delivering and associated video receiving system
    46.
    发明授权
    Video transmitting system with on-the-fly encoding and on-the-fly delivering and associated video receiving system 有权

    公开(公告)号：US10230948B2

    公开(公告)日：2019-03-12

    申请号：US15422425

    申请日：2017-02-01

    Applicant: MEDIATEK INC.

    Inventor： Chia-Yun Cheng ,  Han-Liang Chou ,  Yung-Chang Chang

    IPC: H04N19/10 ,  H04N19/15 ,  H04L1/00 ,  H04N19/423 ,  H04N19/436 ,  H04N19/182

    Abstract: A video transmitting system includes a source buffer, a video encoder, a bitstream buffer, and a transmitting circuit. The source buffer receives pixel data of pixels of a video frame. The video encoder retrieve pixel data of a portion of the pixels of the video frame from the source buffer, and starts encoding the pixel data of the portion of the pixels before pixel data of a last pixel of the video frame is received by the source buffer. The bitstream buffer receives a network abstraction layer (NAL) stream from the video encoder, wherein the NAL stream is generated by encoding the pixel data of the portion of the pixels. The transmitting circuit retrieves the NAL stream from the bitstream buffer, and starts outputting the NAL stream before the pixel data of the last pixel of the video frame is encoded by the video encoder.

    Multi-standard video decoder with novel bin decoding
    47.
    发明授权
    Multi-standard video decoder with novel bin decoding 有权

    公开(公告)号：US10205957B2

    公开(公告)日：2019-02-12

    申请号：US14997691

    申请日：2016-01-18

    Applicant: MediaTek Inc.

    Inventor： Chia-Yun Cheng ,  Sheng-Jen Wang ,  Yung-Chang Chang

    IPC: H04N19/44 ,  H04N19/174 ,  H04N19/91 ,  H04N19/42 ,  H04N19/70

    Abstract: An apparatus for multi-standard bin decoding in a video decoder for decoding two video coded in two different video coding standards is disclosed. The apparatus includes a first bin decoder to decode one or more first bin strings, a second bin decoder to decode one or more second bin strings, a standard change control module coupled to the first bin decoder and the second bin decoder and a system controller coupled to the standard change control module, the first bin decoder and the second bin decoder. The standard change control module or the system controller selects either a next slice or picture to be decoded by the first bin decoder or the second bin decoder based on one or more control parameters including the decoding time information.

    Method and apparatus for arranging pixels of picture in storage units each having storage size not divisible by pixel size
    49.
    发明授权
    Method and apparatus for arranging pixels of picture in storage units each having storage size not divisible by pixel size 有权

    公开(公告)号：US10134107B2

    公开(公告)日：2018-11-20

    申请号：US14226840

    申请日：2014-03-27

    Applicant: MEDIATEK INC.

    Inventor： Chun-Chia Chen ,  Chi-Cheng Ju ,  Yung-Chang Chang ,  Ping Chao

    IPC: G06T1/60 ,  H04N19/51 ,  H04N19/433 ,  G06T7/40

    Abstract: A data arrangement method includes following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; and storing the obtained pixel data of the first N-bit pixels in a plurality of M-bit storage units of a first buffer according to a block-based scan order of the picture. The picture includes a plurality of data blocks, and the block-based scan order includes a raster-scan order for the data blocks. At least one of the M-bit storage units is filled with part of the obtained pixel data of the first N-bit pixels, M and N are positive integers, M is not divisible by N, and the first N-bit pixels include at least one pixel divided into a first part stored in one of the M-bit storage units in the first buffer and a second part stored in another of the M-bit storage units in the first buffer.

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