公开(公告)号：US20180293758A1

公开(公告)日：2018-10-11

申请号：US15482725

申请日：2017-04-08

Applicant: Intel Corporation

Inventor： Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Jeremie Dreyfuss ,  Gal Novik ,  Gal Leibovich ,  Tomer Schwartz ,  Ehud Cohen ,  Lev Faivishevsky ,  Uzi Sarel ,  Amitai Armon ,  Yahav Shadmiy

IPC: G06T9/00

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240419956A1

公开(公告)日：2024-12-19

申请号：US18749806

申请日：2024-06-21

Applicant: Intel Corporation

Inventor： Eran Ben-Avi ,  Neta Zmora ,  Guy Jacob ,  Lev Faivishevsky ,  Jeremie Dreyfuss ,  Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Shira Hirsch ,  Orly Weisel ,  Zigi Walter ,  Yarden Oren

IPC: G06N3/063 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

公开(公告)号：US12131250B2

公开(公告)日：2024-10-29

申请号：US15720982

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ehud Cohen ,  Moshe Maor ,  Ashutosh Parkhi ,  Michael Behar ,  Yaniv Fais

IPC: G06N3/063 ,  G06F16/17 ,  G06F18/21 ,  G06N3/045 ,  G06N3/08 ,  G06V10/44 ,  G06V10/82 ,  G06V10/94

CPC classification number: G06N3/063 ,  G06F16/17 ,  G06F18/21 ,  G06N3/045 ,  G06N3/08 ,  G06V10/454 ,  G06V10/82 ,  G06V10/955

Abstract: A convolutional neural network (CNN) accelerator, including: a CNN circuit for performing a multiple-layer CNN computation, wherein the multiple layers are to receive an input feature according to an input feature map (IFM) and a weight matrix per output feature, wherein an output of a first layer provides an input for a next layer; and a mapping circuit to access a three-dimensional input matrix stored as a Z-major matrix; wherein the CNN circuit is to perform an inner-product direct convolution on the Z-major matrix, wherein the direct convolution lacks a lowering operation.

公开(公告)号：US20240112033A1

公开(公告)日：2024-04-04

申请号：US18514069

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Amit Bleiweiss ,  Itamar Ben-Ari ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jacob Subag ,  Lev Faivishevsky ,  Yaniv Fais ,  Tomer Schwartz

IPC: G06N3/082 ,  G06F8/52 ,  G06F9/445 ,  G06N3/04 ,  G06N3/10 ,  G06N5/04

CPC classification number: G06N3/082 ,  G06F8/52 ,  G06F9/44552 ,  G06N3/04 ,  G06N3/105 ,  G06N5/04 ,  G06N3/084

Abstract: In an example, an apparatus comprises at least one execution platform; and logic, at least partially including hardware logic, to receive a trained neural network model in a model optimizer and convert the trained neural network model to an optimized model comprising parameters that are fit to the at least one execution platform. Other embodiments are also disclosed and claimed.

公开(公告)号：US11886984B2

公开(公告)日：2024-01-30

申请号：US17398302

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06F9/30

CPC classification number: G06N3/063 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30043 ,  G06N3/044 ,  G06N3/045 ,  G06N3/084

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240028883A1

公开(公告)日：2024-01-25

申请号：US18359270

申请日：2023-07-26

Applicant: Intel Corporation

Inventor： Tomer Schwartz ,  Ehud Cohen ,  Uzi Sarel ,  Amitai Armon ,  Yaniv Fais ,  Lev Faivishevsky ,  Amit Bleiweiss ,  Yahav Shadmiy ,  Jacob Subag

IPC: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

公开(公告)号：US20230394305A1

公开(公告)日：2023-12-07

申请号：US18325744

申请日：2023-05-30

Applicant: Intel Corporation

Inventor： Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Jeremie Dreyfuss ,  Amit Bleiweiss ,  Tomer Schwartz ,  Raanan Yonatan Yehezkel Rohekar ,  Michael Behar ,  Amitai Armon ,  Uzi Sarel

IPC: G06N3/08 ,  G06N20/00 ,  G06N20/10

CPC classification number: G06N3/08 ,  G06N20/10 ,  G06N20/00

Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

公开(公告)号：US11669719B2

公开(公告)日：2023-06-06

申请号：US17174864

申请日：2021-02-12

Applicant: Intel Corporation

Inventor： Jeremie Dreyfuss ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Eran Ben-Avi ,  Neta Zmora ,  Tomer Schwartz

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06N3/084 ,  G06V20/56 ,  G06V10/44 ,  G06F18/214 ,  G06N3/044 ,  G06N3/045 ,  G06V10/764 ,  G06V10/82 ,  G06F18/2413

CPC classification number: G06N3/063 ,  G06F18/214 ,  G06F18/24133 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06V10/454 ,  G06V10/764 ,  G06V10/82 ,  G06V20/56

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230067421A1

公开(公告)日：2023-03-02

申请号：US17954846

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Yaniv Fais ,  Moshe Maor

IPC: G06N3/04 ,  G06F17/15 ,  G06F8/41 ,  G06N3/063

Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.

公开(公告)号：US20210350585A1

公开(公告)日：2021-11-11

申请号：US17344639

申请日：2021-06-10

Applicant: INTEL CORPORATION

Inventor： Tomer Bar-On ,  Jacob Subag ,  Yaniv Fais ,  Jeremie Dreyfuss ,  Gal Novik ,  Gal Leibovich ,  Tomer Schwartz ,  Ehud Cohen ,  Lev Faivishevsky ,  Uzi Sarel ,  Amitai Armon ,  Yahav Shadmiy

IPC: G06T9/00 ,  H04N19/42 ,  G06N3/04 ,  H04N19/436 ,  G06N3/08

Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.